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authorLinus Torvalds <torvalds@linux-foundation.org>2018-08-23 16:44:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-08-23 16:44:43 -0400
commit9e259f9352d52053058a234f7c062c4e4f56dc85 (patch)
treebfb1c442e27f95ddb9a04bae2a44ca9e3dd69a85 /include/linux/platform_data
parent5563ae9b39c5ba492be1b18f2d72fd43ba549915 (diff)
parentf0fc40aff6fee100ffbed8328a0df88f8aa75fce (diff)
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 32-bit SoC platform updates from Olof Johansson: "Most of the SoC updates in this cycle are cleanups and moves to more modern infrastructure: - Davinci was moved to common clock framework - OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the keyboard interface (bitbanged AT keyboard via GPIO). - Removal of some stale code for Renesas platforms - Power management improvements for i.MX6LL" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (112 commits) ARM: uniphier: select RESET_CONTROLLER arm64: uniphier: select RESET_CONTROLLER ARM: uniphier: remove empty Makefile ARM: exynos: Clear global variable on init error path ARM: exynos: Remove outdated maintainer information ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15 ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill soc: r9a06g032: don't build SMP files for non-SMP config ARM: shmobile: Add the R9A06G032 SMP enabler driver ARM: at91: pm: configure wakeup sources for ULP1 mode ARM: at91: pm: add PMC fast startup registers defines ARM: at91: pm: Add ULP1 mode support ARM: at91: pm: Use ULP0 naming instead of slow clock ARM: hisi: handle of_iomap and fix missing of_node_put ARM: hisi: check of_iomap and fix missing of_node_put ARM: hisi: fix error handling and missing of_node_put ARM: mx5: Set the DBGEN bit in ARM_GPC register ARM: imx51: Configure M4IF to avoid visual artifacts ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll ARM: imx: fix i.MX6SLL build ...
Diffstat (limited to 'include/linux/platform_data')
-rw-r--r--include/linux/platform_data/ams-delta-fiq.h58
-rw-r--r--include/linux/platform_data/mtd-davinci-aemif.h1
-rw-r--r--include/linux/platform_data/pm33xx.h29
3 files changed, 86 insertions, 2 deletions
diff --git a/include/linux/platform_data/ams-delta-fiq.h b/include/linux/platform_data/ams-delta-fiq.h
new file mode 100644
index 000000000000..cf4589ccb720
--- /dev/null
+++ b/include/linux/platform_data/ams-delta-fiq.h
@@ -0,0 +1,58 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * include/linux/platform_data/ams-delta-fiq.h
5 *
6 * Taken from the original Amstrad modifications to fiq.h
7 *
8 * Copyright (c) 2004 Amstrad Plc
9 * Copyright (c) 2006 Matt Callow
10 * Copyright (c) 2010 Janusz Krzysztofik
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#ifndef __LINUX_PLATFORM_DATA_AMS_DELTA_FIQ_H
17#define __LINUX_PLATFORM_DATA_AMS_DELTA_FIQ_H
18
19/*
20 * These are the offsets from the beginning of the fiq_buffer. They are put here
21 * since the buffer and header need to be accessed by drivers servicing devices
22 * which generate GPIO interrupts - e.g. keyboard, modem, hook switch.
23 */
24#define FIQ_MASK 0
25#define FIQ_STATE 1
26#define FIQ_KEYS_CNT 2
27#define FIQ_TAIL_OFFSET 3
28#define FIQ_HEAD_OFFSET 4
29#define FIQ_BUF_LEN 5
30#define FIQ_KEY 6
31#define FIQ_MISSED_KEYS 7
32#define FIQ_BUFFER_START 8
33#define FIQ_GPIO_INT_MASK 9
34#define FIQ_KEYS_HICNT 10
35#define FIQ_IRQ_PEND 11
36#define FIQ_SIR_CODE_L1 12
37#define IRQ_SIR_CODE_L2 13
38
39#define FIQ_CNT_INT_00 14
40#define FIQ_CNT_INT_KEY 15
41#define FIQ_CNT_INT_MDM 16
42#define FIQ_CNT_INT_03 17
43#define FIQ_CNT_INT_HSW 18
44#define FIQ_CNT_INT_05 19
45#define FIQ_CNT_INT_06 20
46#define FIQ_CNT_INT_07 21
47#define FIQ_CNT_INT_08 22
48#define FIQ_CNT_INT_09 23
49#define FIQ_CNT_INT_10 24
50#define FIQ_CNT_INT_11 25
51#define FIQ_CNT_INT_12 26
52#define FIQ_CNT_INT_13 27
53#define FIQ_CNT_INT_14 28
54#define FIQ_CNT_INT_15 29
55
56#define FIQ_CIRC_BUFF 30 /*Start of circular buffer */
57
58#endif
diff --git a/include/linux/platform_data/mtd-davinci-aemif.h b/include/linux/platform_data/mtd-davinci-aemif.h
index 97948ac2bb9b..a403dd51dacc 100644
--- a/include/linux/platform_data/mtd-davinci-aemif.h
+++ b/include/linux/platform_data/mtd-davinci-aemif.h
@@ -33,5 +33,4 @@ struct davinci_aemif_timing {
33 u8 ta; 33 u8 ta;
34}; 34};
35 35
36int davinci_aemif_setup(struct platform_device *pdev);
37#endif 36#endif
diff --git a/include/linux/platform_data/pm33xx.h b/include/linux/platform_data/pm33xx.h
index f9bed2a0af9d..fbf5ed73c7cc 100644
--- a/include/linux/platform_data/pm33xx.h
+++ b/include/linux/platform_data/pm33xx.h
@@ -12,6 +12,29 @@
12#include <linux/kbuild.h> 12#include <linux/kbuild.h>
13#include <linux/types.h> 13#include <linux/types.h>
14 14
15/*
16 * WFI Flags for sleep code control
17 *
18 * These flags allow PM code to exclude certain operations from happening
19 * in the low level ASM code found in sleep33xx.S and sleep43xx.S
20 *
21 * WFI_FLAG_FLUSH_CACHE: Flush the ARM caches and disable caching. Only
22 * needed when MPU will lose context.
23 * WFI_FLAG_SELF_REFRESH: Let EMIF place DDR memory into self-refresh and
24 * disable EMIF.
25 * WFI_FLAG_SAVE_EMIF: Save context of all EMIF registers and restore in
26 * resume path. Only needed if PER domain loses context
27 * and must also have WFI_FLAG_SELF_REFRESH set.
28 * WFI_FLAG_WAKE_M3: Disable MPU clock or clockdomain to cause wkup_m3 to
29 * execute when WFI instruction executes.
30 * WFI_FLAG_RTC_ONLY: Configure the RTC to enter RTC+DDR mode.
31 */
32#define WFI_FLAG_FLUSH_CACHE BIT(0)
33#define WFI_FLAG_SELF_REFRESH BIT(1)
34#define WFI_FLAG_SAVE_EMIF BIT(2)
35#define WFI_FLAG_WAKE_M3 BIT(3)
36#define WFI_FLAG_RTC_ONLY BIT(4)
37
15#ifndef __ASSEMBLER__ 38#ifndef __ASSEMBLER__
16struct am33xx_pm_sram_addr { 39struct am33xx_pm_sram_addr {
17 void (*do_wfi)(void); 40 void (*do_wfi)(void);
@@ -19,12 +42,15 @@ struct am33xx_pm_sram_addr {
19 unsigned long *resume_offset; 42 unsigned long *resume_offset;
20 unsigned long *emif_sram_table; 43 unsigned long *emif_sram_table;
21 unsigned long *ro_sram_data; 44 unsigned long *ro_sram_data;
45 unsigned long resume_address;
22}; 46};
23 47
24struct am33xx_pm_platform_data { 48struct am33xx_pm_platform_data {
25 int (*init)(void); 49 int (*init)(void);
26 int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long)); 50 int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long),
51 unsigned long args);
27 struct am33xx_pm_sram_addr *(*get_sram_addrs)(void); 52 struct am33xx_pm_sram_addr *(*get_sram_addrs)(void);
53 void __iomem *(*get_rtc_base_addr)(void);
28}; 54};
29 55
30struct am33xx_pm_sram_data { 56struct am33xx_pm_sram_data {
@@ -36,6 +62,7 @@ struct am33xx_pm_sram_data {
36struct am33xx_pm_ro_sram_data { 62struct am33xx_pm_ro_sram_data {
37 u32 amx3_pm_sram_data_virt; 63 u32 amx3_pm_sram_data_virt;
38 u32 amx3_pm_sram_data_phys; 64 u32 amx3_pm_sram_data_phys;
65 void __iomem *rtc_base_virt;
39} __packed __aligned(8); 66} __packed __aligned(8);
40 67
41#endif /* __ASSEMBLER__ */ 68#endif /* __ASSEMBLER__ */