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authorBartosz Folta <bfolta@cadence.com>2016-12-14 01:39:15 -0500
committerDavid S. Miller <davem@davemloft.net>2016-12-17 10:24:33 -0500
commit83a77e9ec4150ee4acc635638f7dedd9da523a26 (patch)
tree7c29f5c99b7221bda73f25ef00ada98ddfaf38d8 /include/linux/platform_data
parent94acf164dc8f1184e8d0737be7125134c2701dbe (diff)
net: macb: Added PCI wrapper for Platform Driver.
There are hardware PCI implementations of Cadence GEM network controller. This patch will allow to use such hardware with reuse of existing Platform Driver. Signed-off-by: Bartosz Folta <bfolta@cadence.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/platform_data')
-rw-r--r--include/linux/platform_data/macb.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/platform_data/macb.h b/include/linux/platform_data/macb.h
index 21b15f6fee25..7815d50c26ff 100644
--- a/include/linux/platform_data/macb.h
+++ b/include/linux/platform_data/macb.h
@@ -8,6 +8,8 @@
8#ifndef __MACB_PDATA_H__ 8#ifndef __MACB_PDATA_H__
9#define __MACB_PDATA_H__ 9#define __MACB_PDATA_H__
10 10
11#include <linux/clk.h>
12
11/** 13/**
12 * struct macb_platform_data - platform data for MACB Ethernet 14 * struct macb_platform_data - platform data for MACB Ethernet
13 * @phy_mask: phy mask passed when register the MDIO bus 15 * @phy_mask: phy mask passed when register the MDIO bus
@@ -15,12 +17,16 @@
15 * @phy_irq_pin: PHY IRQ 17 * @phy_irq_pin: PHY IRQ
16 * @is_rmii: using RMII interface? 18 * @is_rmii: using RMII interface?
17 * @rev_eth_addr: reverse Ethernet address byte order 19 * @rev_eth_addr: reverse Ethernet address byte order
20 * @pclk: platform clock
21 * @hclk: AHB clock
18 */ 22 */
19struct macb_platform_data { 23struct macb_platform_data {
20 u32 phy_mask; 24 u32 phy_mask;
21 int phy_irq_pin; 25 int phy_irq_pin;
22 u8 is_rmii; 26 u8 is_rmii;
23 u8 rev_eth_addr; 27 u8 rev_eth_addr;
28 struct clk *pclk;
29 struct clk *hclk;
24}; 30};
25 31
26#endif /* __MACB_PDATA_H__ */ 32#endif /* __MACB_PDATA_H__ */