diff options
| author | Vinod Koul <vinod.koul@intel.com> | 2015-10-30 22:06:55 -0400 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2015-10-30 22:06:55 -0400 |
| commit | 7d9d43ace29be375d3d1654b688b94029308a1be (patch) | |
| tree | b5dd459d5cd5541636f09342a5d9a08dd3822af8 /include/linux/platform_data | |
| parent | 6df056d8e69a557ac76bc7a88960e4addbc98386 (diff) | |
| parent | e3faf2b8826b8ac58cdaad7f801e59e389320f0e (diff) | |
Merge branch 'topic/edma' into for-linus
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Conflicts:
drivers/dma/edma.c
Diffstat (limited to 'include/linux/platform_data')
| -rw-r--r-- | include/linux/platform_data/edma.h | 104 |
1 files changed, 3 insertions, 101 deletions
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h index bdb2710e2aab..e2878baeb90e 100644 --- a/include/linux/platform_data/edma.h +++ b/include/linux/platform_data/edma.h | |||
| @@ -41,51 +41,6 @@ | |||
| 41 | #ifndef EDMA_H_ | 41 | #ifndef EDMA_H_ |
| 42 | #define EDMA_H_ | 42 | #define EDMA_H_ |
| 43 | 43 | ||
| 44 | /* PaRAM slots are laid out like this */ | ||
| 45 | struct edmacc_param { | ||
| 46 | u32 opt; | ||
| 47 | u32 src; | ||
| 48 | u32 a_b_cnt; | ||
| 49 | u32 dst; | ||
| 50 | u32 src_dst_bidx; | ||
| 51 | u32 link_bcntrld; | ||
| 52 | u32 src_dst_cidx; | ||
| 53 | u32 ccnt; | ||
| 54 | } __packed; | ||
| 55 | |||
| 56 | /* fields in edmacc_param.opt */ | ||
| 57 | #define SAM BIT(0) | ||
| 58 | #define DAM BIT(1) | ||
| 59 | #define SYNCDIM BIT(2) | ||
| 60 | #define STATIC BIT(3) | ||
| 61 | #define EDMA_FWID (0x07 << 8) | ||
| 62 | #define TCCMODE BIT(11) | ||
| 63 | #define EDMA_TCC(t) ((t) << 12) | ||
| 64 | #define TCINTEN BIT(20) | ||
| 65 | #define ITCINTEN BIT(21) | ||
| 66 | #define TCCHEN BIT(22) | ||
| 67 | #define ITCCHEN BIT(23) | ||
| 68 | |||
| 69 | /*ch_status paramater of callback function possible values*/ | ||
| 70 | #define EDMA_DMA_COMPLETE 1 | ||
| 71 | #define EDMA_DMA_CC_ERROR 2 | ||
| 72 | #define EDMA_DMA_TC1_ERROR 3 | ||
| 73 | #define EDMA_DMA_TC2_ERROR 4 | ||
| 74 | |||
| 75 | enum address_mode { | ||
| 76 | INCR = 0, | ||
| 77 | FIFO = 1 | ||
| 78 | }; | ||
| 79 | |||
| 80 | enum fifo_width { | ||
| 81 | W8BIT = 0, | ||
| 82 | W16BIT = 1, | ||
| 83 | W32BIT = 2, | ||
| 84 | W64BIT = 3, | ||
| 85 | W128BIT = 4, | ||
| 86 | W256BIT = 5 | ||
| 87 | }; | ||
| 88 | |||
| 89 | enum dma_event_q { | 44 | enum dma_event_q { |
| 90 | EVENTQ_0 = 0, | 45 | EVENTQ_0 = 0, |
| 91 | EVENTQ_1 = 1, | 46 | EVENTQ_1 = 1, |
| @@ -94,64 +49,10 @@ enum dma_event_q { | |||
| 94 | EVENTQ_DEFAULT = -1 | 49 | EVENTQ_DEFAULT = -1 |
| 95 | }; | 50 | }; |
| 96 | 51 | ||
| 97 | enum sync_dimension { | ||
| 98 | ASYNC = 0, | ||
| 99 | ABSYNC = 1 | ||
| 100 | }; | ||
| 101 | |||
| 102 | #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) | 52 | #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) |
| 103 | #define EDMA_CTLR(i) ((i) >> 16) | 53 | #define EDMA_CTLR(i) ((i) >> 16) |
| 104 | #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) | 54 | #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) |
| 105 | 55 | ||
| 106 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ | ||
| 107 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ | ||
| 108 | #define EDMA_CONT_PARAMS_ANY 1001 | ||
| 109 | #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 | ||
| 110 | #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 | ||
| 111 | |||
| 112 | #define EDMA_MAX_CC 2 | ||
| 113 | |||
| 114 | /* alloc/free DMA channels and their dedicated parameter RAM slots */ | ||
| 115 | int edma_alloc_channel(int channel, | ||
| 116 | void (*callback)(unsigned channel, u16 ch_status, void *data), | ||
| 117 | void *data, enum dma_event_q); | ||
| 118 | void edma_free_channel(unsigned channel); | ||
| 119 | |||
| 120 | /* alloc/free parameter RAM slots */ | ||
| 121 | int edma_alloc_slot(unsigned ctlr, int slot); | ||
| 122 | void edma_free_slot(unsigned slot); | ||
| 123 | |||
| 124 | /* alloc/free a set of contiguous parameter RAM slots */ | ||
| 125 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); | ||
| 126 | int edma_free_cont_slots(unsigned slot, int count); | ||
| 127 | |||
| 128 | /* calls that operate on part of a parameter RAM slot */ | ||
| 129 | void edma_set_src(unsigned slot, dma_addr_t src_port, | ||
| 130 | enum address_mode mode, enum fifo_width); | ||
| 131 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | ||
| 132 | enum address_mode mode, enum fifo_width); | ||
| 133 | dma_addr_t edma_get_position(unsigned slot, bool dst); | ||
| 134 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); | ||
| 135 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); | ||
| 136 | void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, | ||
| 137 | u16 bcnt_rld, enum sync_dimension sync_mode); | ||
| 138 | void edma_link(unsigned from, unsigned to); | ||
| 139 | void edma_unlink(unsigned from); | ||
| 140 | |||
| 141 | /* calls that operate on an entire parameter RAM slot */ | ||
| 142 | void edma_write_slot(unsigned slot, const struct edmacc_param *params); | ||
| 143 | void edma_read_slot(unsigned slot, struct edmacc_param *params); | ||
| 144 | |||
| 145 | /* channel control operations */ | ||
| 146 | int edma_start(unsigned channel); | ||
| 147 | void edma_stop(unsigned channel); | ||
| 148 | void edma_clean_channel(unsigned channel); | ||
| 149 | void edma_clear_event(unsigned channel); | ||
| 150 | void edma_pause(unsigned channel); | ||
| 151 | void edma_resume(unsigned channel); | ||
| 152 | |||
| 153 | void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no); | ||
| 154 | |||
| 155 | struct edma_rsv_info { | 56 | struct edma_rsv_info { |
| 156 | 57 | ||
| 157 | const s16 (*rsv_chans)[2]; | 58 | const s16 (*rsv_chans)[2]; |
| @@ -170,10 +71,11 @@ struct edma_soc_info { | |||
| 170 | /* Resource reservation for other cores */ | 71 | /* Resource reservation for other cores */ |
| 171 | struct edma_rsv_info *rsv; | 72 | struct edma_rsv_info *rsv; |
| 172 | 73 | ||
| 74 | /* List of channels allocated for memcpy, terminated with -1 */ | ||
| 75 | s16 *memcpy_channels; | ||
| 76 | |||
| 173 | s8 (*queue_priority_mapping)[2]; | 77 | s8 (*queue_priority_mapping)[2]; |
| 174 | const s16 (*xbar_chans)[2]; | 78 | const s16 (*xbar_chans)[2]; |
| 175 | }; | 79 | }; |
| 176 | 80 | ||
| 177 | int edma_trigger_channel(unsigned); | ||
| 178 | |||
| 179 | #endif | 81 | #endif |
