Merge tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time we have a very typical update which is mostly fixes and
  updates to drivers and no new drivers.

   - the biggest change is coming from Peter for edma cleanup which even
     caused some last minute regression, things seem settled now
   - idma64 and dw updates
   - iotdma updates
   - module autoload fixes for various drivers
   - scatter gather support for hdmac"

* tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (77 commits)
  dmaengine: edma: Add dummy driver skeleton for edma3-tptc
  Revert "ARM: DTS: am33xx: Use the new DT bindings for the eDMA3"
  Revert "ARM: DTS: am437x: Use the new DT bindings for the eDMA3"
  dmaengine: dw: some Intel devices has no memcpy support
  dmaengine: dw: platform: provide platform data for Intel
  dmaengine: dw: don't override platform data with autocfg
  dmaengine: hdmac: Add scatter-gathered memset support
  dmaengine: hdmac: factorise memset descriptor allocation
  dmaengine: virt-dma: Fix kernel-doc annotations
  ARM: DTS: am437x: Use the new DT bindings for the eDMA3
  ARM: DTS: am33xx: Use the new DT bindings for the eDMA3
  dmaengine: edma: New device tree binding
  dmaengine: Kconfig: edma: Select TI_DMA_CROSSBAR in case of ARCH_OMAP
  dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx
  dmaengine: edma: Merge the of parsing functions
  dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT boot
  dmaengine: edma: Refactor the dma device and channel struct initialization
  dmaengine: edma: Get qDMA channel information from HW also
  dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq
  dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_)
  ...

2 files changed, 5 insertions, 101 deletions

diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 87ac14c584f2..03b6095d3b18 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -37,6 +37,7 @@ struct dw_dma_slave {
  * @nr_channels: Number of channels supported by hardware (max 8)
  * @is_private: The device channels should be marked as private and not for
  *      by the general purpose DMA channel allocator.
+ * @is_memcpy: The device channels do support memory-to-memory transfers.
  * @chan_allocation_order: Allocate channels starting from 0 or 7
  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  * @block_size: Maximum block size supported by the controller
@@ -47,6 +48,7 @@ struct dw_dma_slave {
 struct dw_dma_platform_data {
         unsigned int    nr_channels;
         bool            is_private;
+        bool            is_memcpy;
 #define CHAN_ALLOCATION_ASCENDING       0       /* zero to seven */
 #define CHAN_ALLOCATION_DESCENDING      1       /* seven to zero */
         unsigned char   chan_allocation_order;
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index bdb2710e2aab..e2878baeb90e 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -41,51 +41,6 @@
 #ifndef EDMA_H_
 #define EDMA_H_
 
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
-        u32 opt;
-        u32 src;
-        u32 a_b_cnt;
-        u32 dst;
-        u32 src_dst_bidx;
-        u32 link_bcntrld;
-        u32 src_dst_cidx;
-        u32 ccnt;
-} __packed;
-
-/* fields in edmacc_param.opt */
-#define SAM             BIT(0)
-#define DAM             BIT(1)
-#define SYNCDIM         BIT(2)
-#define STATIC          BIT(3)
-#define EDMA_FWID       (0x07 << 8)
-#define TCCMODE         BIT(11)
-#define EDMA_TCC(t)     ((t) << 12)
-#define TCINTEN         BIT(20)
-#define ITCINTEN        BIT(21)
-#define TCCHEN          BIT(22)
-#define ITCCHEN         BIT(23)
-
-/*ch_status paramater of callback function possible values*/
-#define EDMA_DMA_COMPLETE 1
-#define EDMA_DMA_CC_ERROR 2
-#define EDMA_DMA_TC1_ERROR 3
-#define EDMA_DMA_TC2_ERROR 4
-
-enum address_mode {
-        INCR = 0,
-        FIFO = 1
-};
-
-enum fifo_width {
-        W8BIT = 0,
-        W16BIT = 1,
-        W32BIT = 2,
-        W64BIT = 3,
-        W128BIT = 4,
-        W256BIT = 5
-};
-
 enum dma_event_q {
         EVENTQ_0 = 0,
         EVENTQ_1 = 1,
@@ -94,64 +49,10 @@ enum dma_event_q {
         EVENTQ_DEFAULT = -1
 };
 
-enum sync_dimension {
-        ASYNC = 0,
-        ABSYNC = 1
-};
-
 #define EDMA_CTLR_CHAN(ctlr, chan)      (((ctlr) << 16) | (chan))
 #define EDMA_CTLR(i)                    ((i) >> 16)
 #define EDMA_CHAN_SLOT(i)               ((i) & 0xffff)
 
-#define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY             1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT     1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-#define EDMA_MAX_CC               2
-
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
-        void (*callback)(unsigned channel, u16 ch_status, void *data),
-        void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
-
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
-
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
-/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
-                                enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
-                                 enum address_mode mode, enum fifo_width);
-dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
-                u16 bcnt_rld, enum sync_dimension sync_mode);
-void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
-
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
-
-/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
-
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no);
-
 struct edma_rsv_info {
 
         const s16       (*rsv_chans)[2];
@@ -170,10 +71,11 @@ struct edma_soc_info {
         /* Resource reservation for other cores */
         struct edma_rsv_info    *rsv;
 
+        /* List of channels allocated for memcpy, terminated with -1 */
+        s16                     *memcpy_channels;
+
         s8      (*queue_priority_mapping)[2];
         const s16       (*xbar_chans)[2];
 };
 
-int edma_trigger_channel(unsigned);
-
 #endif