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authorLinus Walleij <linus.walleij@linaro.org>2016-12-18 06:34:55 -0500
committerBoris Brezillon <boris.brezillon@free-electrons.com>2017-01-30 05:50:30 -0500
commit4404d7d821c33ac8105f1d52deb60f736d7c6a06 (patch)
tree4ac19b5d7e9ac8f2b68cf1e0cd424d274d37483c /include/linux/mtd
parent4339b7fdbb90ab579862b0fcde6ee0f342f12692 (diff)
mtd: nand: fsmc: remove stale non-DT probe path
The FSMC driver has an execution path and a header file in <linux/mtd/fsmc.h> that serves to support passing in platform data through board files, albeit no upstream users of this mechanism exist. The header file also contains function headers for functions that do not exist in the kernel. Delete this and move the platform data struct, parsing and handling into the driver, assume we are using OF and make the driver depend on OF, remove the ifdefs making that optional. Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/fsmc.h156
1 files changed, 0 insertions, 156 deletions
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
deleted file mode 100644
index ad3c3488073c..000000000000
--- a/include/linux/mtd/fsmc.h
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * incude/mtd/fsmc.h
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * platform data interface and header file
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#ifndef __MTD_FSMC_H
17#define __MTD_FSMC_H
18
19#include <linux/io.h>
20#include <linux/platform_device.h>
21#include <linux/mtd/physmap.h>
22#include <linux/types.h>
23#include <linux/mtd/partitions.h>
24#include <asm/param.h>
25
26#define FSMC_NAND_BW8 1
27#define FSMC_NAND_BW16 2
28
29#define FSMC_MAX_NOR_BANKS 4
30#define FSMC_MAX_NAND_BANKS 4
31
32#define FSMC_FLASH_WIDTH8 1
33#define FSMC_FLASH_WIDTH16 2
34
35/* fsmc controller registers for NOR flash */
36#define CTRL 0x0
37 /* ctrl register definitions */
38 #define BANK_ENABLE (1 << 0)
39 #define MUXED (1 << 1)
40 #define NOR_DEV (2 << 2)
41 #define WIDTH_8 (0 << 4)
42 #define WIDTH_16 (1 << 4)
43 #define RSTPWRDWN (1 << 6)
44 #define WPROT (1 << 7)
45 #define WRT_ENABLE (1 << 12)
46 #define WAIT_ENB (1 << 13)
47
48#define CTRL_TIM 0x4
49 /* ctrl_tim register definitions */
50
51#define FSMC_NOR_BANK_SZ 0x8
52#define FSMC_NOR_REG_SIZE 0x40
53
54#define FSMC_NOR_REG(base, bank, reg) (base + \
55 FSMC_NOR_BANK_SZ * (bank) + \
56 reg)
57
58/* fsmc controller registers for NAND flash */
59#define PC 0x00
60 /* pc register definitions */
61 #define FSMC_RESET (1 << 0)
62 #define FSMC_WAITON (1 << 1)
63 #define FSMC_ENABLE (1 << 2)
64 #define FSMC_DEVTYPE_NAND (1 << 3)
65 #define FSMC_DEVWID_8 (0 << 4)
66 #define FSMC_DEVWID_16 (1 << 4)
67 #define FSMC_ECCEN (1 << 6)
68 #define FSMC_ECCPLEN_512 (0 << 7)
69 #define FSMC_ECCPLEN_256 (1 << 7)
70 #define FSMC_TCLR_1 (1)
71 #define FSMC_TCLR_SHIFT (9)
72 #define FSMC_TCLR_MASK (0xF)
73 #define FSMC_TAR_1 (1)
74 #define FSMC_TAR_SHIFT (13)
75 #define FSMC_TAR_MASK (0xF)
76#define STS 0x04
77 /* sts register definitions */
78 #define FSMC_CODE_RDY (1 << 15)
79#define COMM 0x08
80 /* comm register definitions */
81 #define FSMC_TSET_0 0
82 #define FSMC_TSET_SHIFT 0
83 #define FSMC_TSET_MASK 0xFF
84 #define FSMC_TWAIT_6 6
85 #define FSMC_TWAIT_SHIFT 8
86 #define FSMC_TWAIT_MASK 0xFF
87 #define FSMC_THOLD_4 4
88 #define FSMC_THOLD_SHIFT 16
89 #define FSMC_THOLD_MASK 0xFF
90 #define FSMC_THIZ_1 1
91 #define FSMC_THIZ_SHIFT 24
92 #define FSMC_THIZ_MASK 0xFF
93#define ATTRIB 0x0C
94#define IOATA 0x10
95#define ECC1 0x14
96#define ECC2 0x18
97#define ECC3 0x1C
98#define FSMC_NAND_BANK_SZ 0x20
99
100#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
101 (FSMC_NAND_BANK_SZ * (bank)) + \
102 reg)
103
104#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
105
106struct fsmc_nand_timings {
107 uint8_t tclr;
108 uint8_t tar;
109 uint8_t thiz;
110 uint8_t thold;
111 uint8_t twait;
112 uint8_t tset;
113};
114
115enum access_mode {
116 USE_DMA_ACCESS = 1,
117 USE_WORD_ACCESS,
118};
119
120/**
121 * fsmc_nand_platform_data - platform specific NAND controller config
122 * @nand_timings: timing setup for the physical NAND interface
123 * @partitions: partition table for the platform, use a default fallback
124 * if this is NULL
125 * @nr_partitions: the number of partitions in the previous entry
126 * @options: different options for the driver
127 * @width: bus width
128 * @bank: default bank
129 * @select_bank: callback to select a certain bank, this is
130 * platform-specific. If the controller only supports one bank
131 * this may be set to NULL
132 */
133struct fsmc_nand_platform_data {
134 struct fsmc_nand_timings *nand_timings;
135 struct mtd_partition *partitions;
136 unsigned int nr_partitions;
137 unsigned int options;
138 unsigned int width;
139 unsigned int bank;
140
141 enum access_mode mode;
142
143 void (*select_bank)(uint32_t bank, uint32_t busw);
144
145 /* priv structures for dma accesses */
146 void *read_dma_priv;
147 void *write_dma_priv;
148};
149
150extern int __init fsmc_nor_init(struct platform_device *pdev,
151 unsigned long base, uint32_t bank, uint32_t width);
152extern void __init fsmc_init_board_info(struct platform_device *pdev,
153 struct mtd_partition *partitions, unsigned int nr_partitions,
154 unsigned int width);
155
156#endif /* __MTD_FSMC_H */
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