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authorUlf Hansson <ulf.hansson@linaro.org>2016-12-30 07:47:20 -0500
committerUlf Hansson <ulf.hansson@linaro.org>2017-02-13 07:19:59 -0500
commit0f21c58c63add705065a75495e7a1860a62470ed (patch)
treedaee06e7251ed94f682e065eba14afcd39405a82 /include/linux/mmc
parentdba4bb484e9e495478f2bcf474393d33f7e0ec27 (diff)
mmc: dw_mmc: Remove the public dw_mmc header file
There are currently no external users of the public dw_mmc header file, except the dw_mmc driver itself. Therefore let's move the definitions from the public dw_mmc header file into the existing private dw_mmc header file and then remove the public one. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'include/linux/mmc')
-rw-r--r--include/linux/mmc/dw_mmc.h274
1 files changed, 0 insertions, 274 deletions
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
deleted file mode 100644
index 15db6f83f53f..000000000000
--- a/include/linux/mmc/dw_mmc.h
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef LINUX_MMC_DW_MMC_H
15#define LINUX_MMC_DW_MMC_H
16
17#include <linux/scatterlist.h>
18#include <linux/mmc/core.h>
19#include <linux/dmaengine.h>
20#include <linux/reset.h>
21
22#define MAX_MCI_SLOTS 2
23
24enum dw_mci_state {
25 STATE_IDLE = 0,
26 STATE_SENDING_CMD,
27 STATE_SENDING_DATA,
28 STATE_DATA_BUSY,
29 STATE_SENDING_STOP,
30 STATE_DATA_ERROR,
31 STATE_SENDING_CMD11,
32 STATE_WAITING_CMD11_DONE,
33};
34
35enum {
36 EVENT_CMD_COMPLETE = 0,
37 EVENT_XFER_COMPLETE,
38 EVENT_DATA_COMPLETE,
39 EVENT_DATA_ERROR,
40};
41
42enum dw_mci_cookie {
43 COOKIE_UNMAPPED,
44 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
45 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
46};
47
48struct mmc_data;
49
50enum {
51 TRANS_MODE_PIO = 0,
52 TRANS_MODE_IDMAC,
53 TRANS_MODE_EDMAC
54};
55
56struct dw_mci_dma_slave {
57 struct dma_chan *ch;
58 enum dma_transfer_direction direction;
59};
60
61/**
62 * struct dw_mci - MMC controller state shared between all slots
63 * @lock: Spinlock protecting the queue and associated data.
64 * @irq_lock: Spinlock protecting the INTMASK setting.
65 * @regs: Pointer to MMIO registers.
66 * @fifo_reg: Pointer to MMIO registers for data FIFO
67 * @sg: Scatterlist entry currently being processed by PIO code, if any.
68 * @sg_miter: PIO mapping scatterlist iterator.
69 * @cur_slot: The slot which is currently using the controller.
70 * @mrq: The request currently being processed on @cur_slot,
71 * or NULL if the controller is idle.
72 * @cmd: The command currently being sent to the card, or NULL.
73 * @data: The data currently being transferred, or NULL if no data
74 * transfer is in progress.
75 * @stop_abort: The command currently prepared for stoping transfer.
76 * @prev_blksz: The former transfer blksz record.
77 * @timing: Record of current ios timing.
78 * @use_dma: Whether DMA channel is initialized or not.
79 * @using_dma: Whether DMA is in use for the current transfer.
80 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
81 * @sg_dma: Bus address of DMA buffer.
82 * @sg_cpu: Virtual address of DMA buffer.
83 * @dma_ops: Pointer to platform-specific DMA callbacks.
84 * @cmd_status: Snapshot of SR taken upon completion of the current
85 * @ring_size: Buffer size for idma descriptors.
86 * command. Only valid when EVENT_CMD_COMPLETE is pending.
87 * @dms: structure of slave-dma private data.
88 * @phy_regs: physical address of controller's register map
89 * @data_status: Snapshot of SR taken upon completion of the current
90 * data transfer. Only valid when EVENT_DATA_COMPLETE or
91 * EVENT_DATA_ERROR is pending.
92 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
93 * to be sent.
94 * @dir_status: Direction of current transfer.
95 * @tasklet: Tasklet running the request state machine.
96 * @pending_events: Bitmask of events flagged by the interrupt handler
97 * to be processed by the tasklet.
98 * @completed_events: Bitmask of events which the state machine has
99 * processed.
100 * @state: Tasklet state.
101 * @queue: List of slots waiting for access to the controller.
102 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
103 * rate and timeout calculations.
104 * @current_speed: Configured rate of the controller.
105 * @num_slots: Number of slots available.
106 * @fifoth_val: The value of FIFOTH register.
107 * @verid: Denote Version ID.
108 * @dev: Device associated with the MMC controller.
109 * @pdata: Platform data associated with the MMC controller.
110 * @drv_data: Driver specific data for identified variant of the controller
111 * @priv: Implementation defined private data.
112 * @biu_clk: Pointer to bus interface unit clock instance.
113 * @ciu_clk: Pointer to card interface unit clock instance.
114 * @slot: Slots sharing this MMC controller.
115 * @fifo_depth: depth of FIFO.
116 * @data_shift: log2 of FIFO item size.
117 * @part_buf_start: Start index in part_buf.
118 * @part_buf_count: Bytes of partial data in part_buf.
119 * @part_buf: Simple buffer for partial fifo reads/writes.
120 * @push_data: Pointer to FIFO push function.
121 * @pull_data: Pointer to FIFO pull function.
122 * @vqmmc_enabled: Status of vqmmc, should be true or false.
123 * @irq_flags: The flags to be passed to request_irq.
124 * @irq: The irq value to be passed to request_irq.
125 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
126 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
127 * @dto_timer: Timer for broken data transfer over scheme.
128 *
129 * Locking
130 * =======
131 *
132 * @lock is a softirq-safe spinlock protecting @queue as well as
133 * @cur_slot, @mrq and @state. These must always be updated
134 * at the same time while holding @lock.
135 *
136 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
137 * to allow the interrupt handler to modify it directly. Held for only long
138 * enough to read-modify-write INTMASK and no other locks are grabbed when
139 * holding this one.
140 *
141 * The @mrq field of struct dw_mci_slot is also protected by @lock,
142 * and must always be written at the same time as the slot is added to
143 * @queue.
144 *
145 * @pending_events and @completed_events are accessed using atomic bit
146 * operations, so they don't need any locking.
147 *
148 * None of the fields touched by the interrupt handler need any
149 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
150 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
151 * interrupts must be disabled and @data_status updated with a
152 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
153 * CMDRDY interrupt must be disabled and @cmd_status updated with a
154 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
155 * bytes_xfered field of @data must be written. This is ensured by
156 * using barriers.
157 */
158struct dw_mci {
159 spinlock_t lock;
160 spinlock_t irq_lock;
161 void __iomem *regs;
162 void __iomem *fifo_reg;
163
164 struct scatterlist *sg;
165 struct sg_mapping_iter sg_miter;
166
167 struct dw_mci_slot *cur_slot;
168 struct mmc_request *mrq;
169 struct mmc_command *cmd;
170 struct mmc_data *data;
171 struct mmc_command stop_abort;
172 unsigned int prev_blksz;
173 unsigned char timing;
174
175 /* DMA interface members*/
176 int use_dma;
177 int using_dma;
178 int dma_64bit_address;
179
180 dma_addr_t sg_dma;
181 void *sg_cpu;
182 const struct dw_mci_dma_ops *dma_ops;
183 /* For idmac */
184 unsigned int ring_size;
185
186 /* For edmac */
187 struct dw_mci_dma_slave *dms;
188 /* Registers's physical base address */
189 resource_size_t phy_regs;
190
191 u32 cmd_status;
192 u32 data_status;
193 u32 stop_cmdr;
194 u32 dir_status;
195 struct tasklet_struct tasklet;
196 unsigned long pending_events;
197 unsigned long completed_events;
198 enum dw_mci_state state;
199 struct list_head queue;
200
201 u32 bus_hz;
202 u32 current_speed;
203 u32 num_slots;
204 u32 fifoth_val;
205 u16 verid;
206 struct device *dev;
207 struct dw_mci_board *pdata;
208 const struct dw_mci_drv_data *drv_data;
209 void *priv;
210 struct clk *biu_clk;
211 struct clk *ciu_clk;
212 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
213
214 /* FIFO push and pull */
215 int fifo_depth;
216 int data_shift;
217 u8 part_buf_start;
218 u8 part_buf_count;
219 union {
220 u16 part_buf16;
221 u32 part_buf32;
222 u64 part_buf;
223 };
224 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
225 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
226
227 bool vqmmc_enabled;
228 unsigned long irq_flags; /* IRQ flags */
229 int irq;
230
231 int sdio_id0;
232
233 struct timer_list cmd11_timer;
234 struct timer_list dto_timer;
235};
236
237/* DMA ops for Internal/External DMAC interface */
238struct dw_mci_dma_ops {
239 /* DMA Ops */
240 int (*init)(struct dw_mci *host);
241 int (*start)(struct dw_mci *host, unsigned int sg_len);
242 void (*complete)(void *host);
243 void (*stop)(struct dw_mci *host);
244 void (*cleanup)(struct dw_mci *host);
245 void (*exit)(struct dw_mci *host);
246};
247
248struct dma_pdata;
249
250/* Board platform data */
251struct dw_mci_board {
252 u32 num_slots;
253
254 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
255
256 u32 caps; /* Capabilities */
257 u32 caps2; /* More capabilities */
258 u32 pm_caps; /* PM capabilities */
259 /*
260 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
261 * but note that this may not be reliable after a bootloader has used
262 * it.
263 */
264 unsigned int fifo_depth;
265
266 /* delay in mS before detecting cards after interrupt */
267 u32 detect_delay_ms;
268
269 struct reset_control *rstc;
270 struct dw_mci_dma_ops *dma_ops;
271 struct dma_pdata *data;
272};
273
274#endif /* LINUX_MMC_DW_MMC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 23:56:35 -0400