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authorLinus Torvalds <torvalds@linux-foundation.org>2017-05-03 15:16:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2017-05-03 15:16:25 -0400
commitd26f552ebbfb0f2c7fe712f457a038d60ed73daa (patch)
tree8d13c7344cabc99e738e0db7262b713708026fa0 /include/linux/mfd
parente897f267c51812bfecec45771a2d835c1a2bdacf (diff)
parentab6241ae07c3c698543b565e4ea41995a29a3f62 (diff)
Merge tag 'mfd-next-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "New Drivers: - Freescale MXS Low Resolution ADC - Freescale i.MX23/i.MX28 LRADC touchscreen - Motorola CPCAP Power Button - TI LMU (Lighting Management Unit) - Atmel SMC (Static Memory Controller) New Device Support: - Add support for X-Powers AXP803 to axp20x - Add support for Dialog Semi DA9061 to da9062-core - Add support for Intel Cougar Mountain to lpc_ich - Add support for Intel Gemini Lake to lpc_ich New Functionality: - Add Device Tree support; wm831x-*, axp20x, ti-lmu, da9062, sun4i-gpadc - Add IRQ sense support; motorola-cpcap - Add ACPI support; cros_ec - Add Reset support; altera-a10sr - Add ADC support; axp20x - Add AC Power support; axp20x - Add Runtime PM support; atmel-ebi, exynos-lpass - Add Battery Power Supply support; axp20x - Add Clock support; exynos-lpass, hi655x-pmic Fix-ups: - Implicitly specify required headers; motorola-cpcap, intel_soc_pmic_bxtwc - Add .remove() method; stm32-timers, exynos-lpass - Remove unused code; intel_soc_pmic_core, intel-lpss-acpi, ipaq-micro, atmel-smc, menelaus - Rename variables for clarity; axp20x - Convert pr_warning() to pr_warn(); db8500-prcmu, sta2x11-mfd, twl4030-power - Improve formatting; arizona-core, axp20x - Use raw_spinlock_*() variants; asic3, t7l66xb, tc6393xb - Simplify/refactor code; arizona-core, atmel-ebi - Improve error checking; intel_soc_pmic_core Bug Fixes: - Ensure OMAP3630/3730 boards can successfully reboot; twl4030-power - Correct max-register value; stm32-timers - Extend timeout to account for clock stretching; cros_ec_spi - Use correct IRQ trigger type; motorola-cpcap - Fix bad use of IRQ sense register; motorola-cpcap - Logic error "||" should be "&&"; mxs-lradc-ts" * tag 'mfd-next-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (79 commits) input: touchscreen: mxs-lradc: || vs && typos dt-bindings: Add AXP803's regulator info mfd: axp20x: Support AXP803 variant dt-bindings: Add device tree binding for X-Powers AXP803 PMIC dt-bindings: Make AXP20X compatible strings one per line mfd: intel_soc_pmic_core: Fix unchecked return value mfd: menelaus: Remove obsolete local_irq_disable() and local_irq_enable() mfd: omap-usb-tll: Configure ULPIAUTOIDLE mfd: omap-usb-tll: Fix inverted bit use for USB TLL mode mfd: palmas: Fixed spelling mistake in error message mfd: lpc_ich: Add support for Intel Gemini Lake SoC mfd: hi655x: Add the clock cell to provide WiFi and Bluetooth mfd: intel_soc_pmic: Fix a mess with compilation units mfd: exynos-lpass: Add runtime PM support mfd: exynos-lpass: Add missing remove() function mfd: exynos-lpass: Add support for clocks mfd: exynos-lpass: Remove pad retention control iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs mfd: cpcap: Fix bad use of IRQ sense register mfd: cpcap: Use ack_invert interrupts ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/axp20x.h44
-rw-r--r--include/linux/mfd/cros_ec.h18
-rw-r--r--include/linux/mfd/da9062/core.h29
-rw-r--r--include/linux/mfd/da9062/registers.h5
-rw-r--r--include/linux/mfd/intel_soc_pmic_bxtwc.h (renamed from include/linux/mfd/intel_bxtwc.h)4
-rw-r--r--include/linux/mfd/motorola-cpcap.h2
-rw-r--r--include/linux/mfd/mxs-lradc.h187
-rw-r--r--include/linux/mfd/syscon/atmel-smc.h237
-rw-r--r--include/linux/mfd/syscon/exynos5-pmu.h3
-rw-r--r--include/linux/mfd/ti-lmu-register.h280
-rw-r--r--include/linux/mfd/ti-lmu.h87
-rw-r--r--include/linux/mfd/wm831x/core.h9
12 files changed, 740 insertions, 165 deletions
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 0d9a1ff38393..cde56cfe8446 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -20,6 +20,7 @@ enum axp20x_variants {
20 AXP221_ID, 20 AXP221_ID,
21 AXP223_ID, 21 AXP223_ID,
22 AXP288_ID, 22 AXP288_ID,
23 AXP803_ID,
23 AXP806_ID, 24 AXP806_ID,
24 AXP809_ID, 25 AXP809_ID,
25 NR_AXP20X_VARIANTS, 26 NR_AXP20X_VARIANTS,
@@ -228,13 +229,13 @@ enum axp20x_variants {
228#define AXP20X_OCV_MAX 0xf 229#define AXP20X_OCV_MAX 0xf
229 230
230/* AXP22X specific registers */ 231/* AXP22X specific registers */
231#define AXP22X_PMIC_ADC_H 0x56 232#define AXP22X_PMIC_TEMP_H 0x56
232#define AXP22X_PMIC_ADC_L 0x57 233#define AXP22X_PMIC_TEMP_L 0x57
233#define AXP22X_TS_ADC_H 0x58 234#define AXP22X_TS_ADC_H 0x58
234#define AXP22X_TS_ADC_L 0x59 235#define AXP22X_TS_ADC_L 0x59
235#define AXP22X_BATLOW_THRES1 0xe6 236#define AXP22X_BATLOW_THRES1 0xe6
236 237
237/* AXP288 specific registers */ 238/* AXP288/AXP803 specific registers */
238#define AXP288_POWER_REASON 0x02 239#define AXP288_POWER_REASON 0x02
239#define AXP288_BC_GLOBAL 0x2c 240#define AXP288_BC_GLOBAL 0x2c
240#define AXP288_BC_VBUS_CNTL 0x2d 241#define AXP288_BC_VBUS_CNTL 0x2d
@@ -475,6 +476,43 @@ enum axp288_irqs {
475 AXP288_IRQ_BC_USB_CHNG, 476 AXP288_IRQ_BC_USB_CHNG,
476}; 477};
477 478
479enum axp803_irqs {
480 AXP803_IRQ_ACIN_OVER_V = 1,
481 AXP803_IRQ_ACIN_PLUGIN,
482 AXP803_IRQ_ACIN_REMOVAL,
483 AXP803_IRQ_VBUS_OVER_V,
484 AXP803_IRQ_VBUS_PLUGIN,
485 AXP803_IRQ_VBUS_REMOVAL,
486 AXP803_IRQ_BATT_PLUGIN,
487 AXP803_IRQ_BATT_REMOVAL,
488 AXP803_IRQ_BATT_ENT_ACT_MODE,
489 AXP803_IRQ_BATT_EXIT_ACT_MODE,
490 AXP803_IRQ_CHARG,
491 AXP803_IRQ_CHARG_DONE,
492 AXP803_IRQ_BATT_CHG_TEMP_HIGH,
493 AXP803_IRQ_BATT_CHG_TEMP_HIGH_END,
494 AXP803_IRQ_BATT_CHG_TEMP_LOW,
495 AXP803_IRQ_BATT_CHG_TEMP_LOW_END,
496 AXP803_IRQ_BATT_ACT_TEMP_HIGH,
497 AXP803_IRQ_BATT_ACT_TEMP_HIGH_END,
498 AXP803_IRQ_BATT_ACT_TEMP_LOW,
499 AXP803_IRQ_BATT_ACT_TEMP_LOW_END,
500 AXP803_IRQ_DIE_TEMP_HIGH,
501 AXP803_IRQ_GPADC,
502 AXP803_IRQ_LOW_PWR_LVL1,
503 AXP803_IRQ_LOW_PWR_LVL2,
504 AXP803_IRQ_TIMER,
505 AXP803_IRQ_PEK_RIS_EDGE,
506 AXP803_IRQ_PEK_FAL_EDGE,
507 AXP803_IRQ_PEK_SHORT,
508 AXP803_IRQ_PEK_LONG,
509 AXP803_IRQ_PEK_OVER_OFF,
510 AXP803_IRQ_GPIO1_INPUT,
511 AXP803_IRQ_GPIO0_INPUT,
512 AXP803_IRQ_BC_USB_CHNG,
513 AXP803_IRQ_MV_CHNG,
514};
515
478enum axp806_irqs { 516enum axp806_irqs {
479 AXP806_IRQ_DIE_TEMP_HIGH_LV1, 517 AXP806_IRQ_DIE_TEMP_HIGH_LV1,
480 AXP806_IRQ_DIE_TEMP_HIGH_LV2, 518 AXP806_IRQ_DIE_TEMP_HIGH_LV2,
diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
index 3eef9fb9968a..28baee63eaf6 100644
--- a/include/linux/mfd/cros_ec.h
+++ b/include/linux/mfd/cros_ec.h
@@ -305,4 +305,22 @@ extern struct attribute_group cros_ec_attr_group;
305extern struct attribute_group cros_ec_lightbar_attr_group; 305extern struct attribute_group cros_ec_lightbar_attr_group;
306extern struct attribute_group cros_ec_vbc_attr_group; 306extern struct attribute_group cros_ec_vbc_attr_group;
307 307
308/* ACPI GPE handler */
309#ifdef CONFIG_ACPI
310
311int cros_ec_acpi_install_gpe_handler(struct device *dev);
312void cros_ec_acpi_remove_gpe_handler(void);
313void cros_ec_acpi_clear_gpe(void);
314
315#else /* CONFIG_ACPI */
316
317static inline int cros_ec_acpi_install_gpe_handler(struct device *dev)
318{
319 return -ENODEV;
320}
321static inline void cros_ec_acpi_remove_gpe_handler(void) {}
322static inline void cros_ec_acpi_clear_gpe(void) {}
323
324#endif /* CONFIG_ACPI */
325
308#endif /* __LINUX_MFD_CROS_EC_H */ 326#endif /* __LINUX_MFD_CROS_EC_H */
diff --git a/include/linux/mfd/da9062/core.h b/include/linux/mfd/da9062/core.h
index 376ba84366a0..74d33a01ddae 100644
--- a/include/linux/mfd/da9062/core.h
+++ b/include/linux/mfd/da9062/core.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2015 Dialog Semiconductor Ltd. 2 * Copyright (C) 2015-2017 Dialog Semiconductor
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -18,7 +18,31 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/mfd/da9062/registers.h> 19#include <linux/mfd/da9062/registers.h>
20 20
21/* Interrupts */ 21enum da9062_compatible_types {
22 COMPAT_TYPE_DA9061 = 1,
23 COMPAT_TYPE_DA9062,
24};
25
26enum da9061_irqs {
27 /* IRQ A */
28 DA9061_IRQ_ONKEY,
29 DA9061_IRQ_WDG_WARN,
30 DA9061_IRQ_SEQ_RDY,
31 /* IRQ B*/
32 DA9061_IRQ_TEMP,
33 DA9061_IRQ_LDO_LIM,
34 DA9061_IRQ_DVC_RDY,
35 DA9061_IRQ_VDD_WARN,
36 /* IRQ C */
37 DA9061_IRQ_GPI0,
38 DA9061_IRQ_GPI1,
39 DA9061_IRQ_GPI2,
40 DA9061_IRQ_GPI3,
41 DA9061_IRQ_GPI4,
42
43 DA9061_NUM_IRQ,
44};
45
22enum da9062_irqs { 46enum da9062_irqs {
23 /* IRQ A */ 47 /* IRQ A */
24 DA9062_IRQ_ONKEY, 48 DA9062_IRQ_ONKEY,
@@ -45,6 +69,7 @@ struct da9062 {
45 struct device *dev; 69 struct device *dev;
46 struct regmap *regmap; 70 struct regmap *regmap;
47 struct regmap_irq_chip_data *regmap_irq; 71 struct regmap_irq_chip_data *regmap_irq;
72 enum da9062_compatible_types chip_type;
48}; 73};
49 74
50#endif /* __MFD_DA9062_CORE_H__ */ 75#endif /* __MFD_DA9062_CORE_H__ */
diff --git a/include/linux/mfd/da9062/registers.h b/include/linux/mfd/da9062/registers.h
index 97790d1b02c5..18d576aed902 100644
--- a/include/linux/mfd/da9062/registers.h
+++ b/include/linux/mfd/da9062/registers.h
@@ -1,6 +1,5 @@
1/* 1/*
2 * registers.h - REGISTERS H for DA9062 2 * Copyright (C) 2015-2017 Dialog Semiconductor
3 * Copyright (C) 2015 Dialog Semiconductor Ltd.
4 * 3 *
5 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -18,6 +17,8 @@
18 17
19#define DA9062_PMIC_DEVICE_ID 0x62 18#define DA9062_PMIC_DEVICE_ID 0x62
20#define DA9062_PMIC_VARIANT_MRC_AA 0x01 19#define DA9062_PMIC_VARIANT_MRC_AA 0x01
20#define DA9062_PMIC_VARIANT_VRC_DA9061 0x01
21#define DA9062_PMIC_VARIANT_VRC_DA9062 0x02
21 22
22#define DA9062_I2C_PAGE_SEL_SHIFT 1 23#define DA9062_I2C_PAGE_SEL_SHIFT 1
23 24
diff --git a/include/linux/mfd/intel_bxtwc.h b/include/linux/mfd/intel_soc_pmic_bxtwc.h
index 1a0ee9d6efe9..0c351bc85d2d 100644
--- a/include/linux/mfd/intel_bxtwc.h
+++ b/include/linux/mfd/intel_soc_pmic_bxtwc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * intel_bxtwc.h - Header file for Intel Broxton Whiskey Cove PMIC 2 * Header file for Intel Broxton Whiskey Cove PMIC
3 * 3 *
4 * Copyright (C) 2015 Intel Corporation. All rights reserved. 4 * Copyright (C) 2015 Intel Corporation. All rights reserved.
5 * 5 *
@@ -13,8 +13,6 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <linux/mfd/intel_soc_pmic.h>
17
18#ifndef __INTEL_BXTWC_H__ 16#ifndef __INTEL_BXTWC_H__
19#define __INTEL_BXTWC_H__ 17#define __INTEL_BXTWC_H__
20 18
diff --git a/include/linux/mfd/motorola-cpcap.h b/include/linux/mfd/motorola-cpcap.h
index 53758a7d7c32..aefc49cb7ba9 100644
--- a/include/linux/mfd/motorola-cpcap.h
+++ b/include/linux/mfd/motorola-cpcap.h
@@ -293,3 +293,5 @@ static inline int cpcap_get_vendor(struct device *dev,
293 293
294 return 0; 294 return 0;
295} 295}
296
297extern int cpcap_sense_virq(struct regmap *regmap, int virq);
diff --git a/include/linux/mfd/mxs-lradc.h b/include/linux/mfd/mxs-lradc.h
new file mode 100644
index 000000000000..661a4521f723
--- /dev/null
+++ b/include/linux/mfd/mxs-lradc.h
@@ -0,0 +1,187 @@
1/*
2 * Freescale MXS Low Resolution Analog-to-Digital Converter driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Copyright (c) 2016 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
6 *
7 * Author: Marek Vasut <marex@denx.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#ifndef __MFD_MXS_LRADC_H
21#define __MFD_MXS_LRADC_H
22
23#include <linux/bitops.h>
24#include <linux/io.h>
25#include <linux/stmp_device.h>
26
27#define LRADC_MAX_DELAY_CHANS 4
28#define LRADC_MAX_MAPPED_CHANS 8
29#define LRADC_MAX_TOTAL_CHANS 16
30
31#define LRADC_DELAY_TIMER_HZ 2000
32
33#define LRADC_CTRL0 0x00
34# define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23)
35# define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22)
36# define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21)
37# define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20)
38# define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19)
39# define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18)
40# define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17)
41# define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16)
42
43# define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20)
44# define LRADC_CTRL0_MX23_YM BIT(19)
45# define LRADC_CTRL0_MX23_XM BIT(18)
46# define LRADC_CTRL0_MX23_YP BIT(17)
47# define LRADC_CTRL0_MX23_XP BIT(16)
48
49# define LRADC_CTRL0_MX28_PLATE_MASK \
50 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
51 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
52 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
53 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
54
55# define LRADC_CTRL0_MX23_PLATE_MASK \
56 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
57 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
58 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
59
60#define LRADC_CTRL1 0x10
61#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24)
62#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
63#define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
64#define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
65#define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
66#define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8)
67#define LRADC_CTRL1_LRADC_IRQ(n) BIT(n)
68#define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
69#define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
70#define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
71
72#define LRADC_CTRL2 0x20
73#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
74#define LRADC_CTRL2_TEMPSENSE_PWD BIT(15)
75
76#define LRADC_STATUS 0x40
77#define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
78
79#define LRADC_CH(n) (0x50 + (0x10 * (n)))
80#define LRADC_CH_ACCUMULATE BIT(29)
81#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
82#define LRADC_CH_NUM_SAMPLES_OFFSET 24
83#define LRADC_CH_NUM_SAMPLES(x) \
84 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
85#define LRADC_CH_VALUE_MASK 0x3ffff
86#define LRADC_CH_VALUE_OFFSET 0
87
88#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
89#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24)
90#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
91#define LRADC_DELAY_TRIGGER(x) \
92 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
93 LRADC_DELAY_TRIGGER_LRADCS_MASK)
94#define LRADC_DELAY_KICK BIT(20)
95#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
96#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
97#define LRADC_DELAY_TRIGGER_DELAYS(x) \
98 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
99 LRADC_DELAY_TRIGGER_DELAYS_MASK)
100#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
101#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
102#define LRADC_DELAY_LOOP(x) \
103 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
104 LRADC_DELAY_LOOP_COUNT_MASK)
105#define LRADC_DELAY_DELAY_MASK 0x7ff
106#define LRADC_DELAY_DELAY_OFFSET 0
107#define LRADC_DELAY_DELAY(x) \
108 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
109 LRADC_DELAY_DELAY_MASK)
110
111#define LRADC_CTRL4 0x140
112#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
113#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
114#define LRADC_CTRL4_LRADCSELECT(n, x) \
115 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
116 LRADC_CTRL4_LRADCSELECT_MASK(n))
117
118#define LRADC_RESOLUTION 12
119#define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
120
121#define BUFFER_VCHANS_LIMITED 0x3f
122#define BUFFER_VCHANS_ALL 0xff
123
124 /*
125 * Certain LRADC channels are shared between touchscreen
126 * and/or touch-buttons and generic LRADC block. Therefore when using
127 * either of these, these channels are not available for the regular
128 * sampling. The shared channels are as follows:
129 *
130 * CH0 -- Touch button #0
131 * CH1 -- Touch button #1
132 * CH2 -- Touch screen XPUL
133 * CH3 -- Touch screen YPLL
134 * CH4 -- Touch screen XNUL
135 * CH5 -- Touch screen YNLR
136 * CH6 -- Touch screen WIPER (5-wire only)
137 *
138 * The bit fields below represents which parts of the LRADC block are
139 * switched into special mode of operation. These channels can not
140 * be sampled as regular LRADC channels. The driver will refuse any
141 * attempt to sample these channels.
142 */
143#define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0))
144#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
145#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
146
147enum mxs_lradc_id {
148 IMX23_LRADC,
149 IMX28_LRADC,
150};
151
152enum mxs_lradc_ts_wires {
153 MXS_LRADC_TOUCHSCREEN_NONE = 0,
154 MXS_LRADC_TOUCHSCREEN_4WIRE,
155 MXS_LRADC_TOUCHSCREEN_5WIRE,
156};
157
158/**
159 * struct mxs_lradc
160 * @soc: soc type (IMX23 or IMX28)
161 * @clk: 2 kHz clock for delay units
162 * @buffer_vchans: channels that can be used during buffered capture
163 * @touchscreen_wire: touchscreen type (4-wire or 5-wire)
164 * @use_touchbutton: button state (on or off)
165 */
166struct mxs_lradc {
167 enum mxs_lradc_id soc;
168 struct clk *clk;
169 u8 buffer_vchans;
170
171 enum mxs_lradc_ts_wires touchscreen_wire;
172 bool use_touchbutton;
173};
174
175static inline u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
176{
177 switch (lradc->soc) {
178 case IMX23_LRADC:
179 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
180 case IMX28_LRADC:
181 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
182 default:
183 return 0;
184 }
185}
186
187#endif /* __MXS_LRADC_H */
diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h
index be6ebe64eebe..afa266169800 100644
--- a/include/linux/mfd/syscon/atmel-smc.h
+++ b/include/linux/mfd/syscon/atmel-smc.h
@@ -17,157 +17,92 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/regmap.h> 18#include <linux/regmap.h>
19 19
20#define AT91SAM9_SMC_GENERIC 0x00 20#define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
21#define AT91SAM9_SMC_GENERIC_BLK_SZ 0x10 21#define ATMEL_HSMC_SETUP(cs) (0x600 + ((cs) * 0x14))
22 22#define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
23#define SAMA5_SMC_GENERIC 0x600 23#define ATMEL_HSMC_PULSE(cs) (0x600 + ((cs) * 0x14) + 0x4)
24#define SAMA5_SMC_GENERIC_BLK_SZ 0x14 24#define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
25 25#define ATMEL_HSMC_CYCLE(cs) (0x600 + ((cs) * 0x14) + 0x8)
26#define AT91SAM9_SMC_SETUP(o) ((o) + 0x00) 26#define ATMEL_SMC_NWE_SHIFT 0
27#define AT91SAM9_SMC_NWESETUP(x) (x) 27#define ATMEL_SMC_NCS_WR_SHIFT 8
28#define AT91SAM9_SMC_NCS_WRSETUP(x) ((x) << 8) 28#define ATMEL_SMC_NRD_SHIFT 16
29#define AT91SAM9_SMC_NRDSETUP(x) ((x) << 16) 29#define ATMEL_SMC_NCS_RD_SHIFT 24
30#define AT91SAM9_SMC_NCS_NRDSETUP(x) ((x) << 24) 30
31 31#define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
32#define AT91SAM9_SMC_PULSE(o) ((o) + 0x04) 32#define ATMEL_HSMC_MODE(cs) (0x600 + ((cs) * 0x14) + 0x10)
33#define AT91SAM9_SMC_NWEPULSE(x) (x) 33#define ATMEL_SMC_MODE_READMODE_MASK BIT(0)
34#define AT91SAM9_SMC_NCS_WRPULSE(x) ((x) << 8) 34#define ATMEL_SMC_MODE_READMODE_NCS (0 << 0)
35#define AT91SAM9_SMC_NRDPULSE(x) ((x) << 16) 35#define ATMEL_SMC_MODE_READMODE_NRD (1 << 0)
36#define AT91SAM9_SMC_NCS_NRDPULSE(x) ((x) << 24) 36#define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1)
37 37#define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1)
38#define AT91SAM9_SMC_CYCLE(o) ((o) + 0x08) 38#define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1)
39#define AT91SAM9_SMC_NWECYCLE(x) (x) 39#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)
40#define AT91SAM9_SMC_NRDCYCLE(x) ((x) << 16) 40#define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4)
41 41#define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4)
42#define AT91SAM9_SMC_MODE(o) ((o) + 0x0c) 42#define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4)
43#define SAMA5_SMC_MODE(o) ((o) + 0x10) 43#define ATMEL_SMC_MODE_BAT_MASK BIT(8)
44#define AT91_SMC_READMODE BIT(0) 44#define ATMEL_SMC_MODE_BAT_SELECT (0 << 8)
45#define AT91_SMC_READMODE_NCS (0 << 0) 45#define ATMEL_SMC_MODE_BAT_WRITE (1 << 8)
46#define AT91_SMC_READMODE_NRD (1 << 0) 46#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)
47#define AT91_SMC_WRITEMODE BIT(1) 47#define ATMEL_SMC_MODE_DBW_8 (0 << 12)
48#define AT91_SMC_WRITEMODE_NCS (0 << 1) 48#define ATMEL_SMC_MODE_DBW_16 (1 << 12)
49#define AT91_SMC_WRITEMODE_NWE (1 << 1) 49#define ATMEL_SMC_MODE_DBW_32 (2 << 12)
50#define AT91_SMC_EXNWMODE GENMASK(5, 4) 50#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)
51#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) 51#define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
52#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) 52#define ATMEL_SMC_MODE_TDF_MAX 16
53#define AT91_SMC_EXNWMODE_READY (3 << 4) 53#define ATMEL_SMC_MODE_TDF_MIN 1
54#define AT91_SMC_BAT BIT(8) 54#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20)
55#define AT91_SMC_BAT_SELECT (0 << 8) 55#define ATMEL_SMC_MODE_PMEN BIT(24)
56#define AT91_SMC_BAT_WRITE (1 << 8) 56#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
57#define AT91_SMC_DBW GENMASK(13, 12) 57#define ATMEL_SMC_MODE_PS_4 (0 << 28)
58#define AT91_SMC_DBW_8 (0 << 12) 58#define ATMEL_SMC_MODE_PS_8 (1 << 28)
59#define AT91_SMC_DBW_16 (1 << 12) 59#define ATMEL_SMC_MODE_PS_16 (2 << 28)
60#define AT91_SMC_DBW_32 (2 << 12) 60#define ATMEL_SMC_MODE_PS_32 (3 << 28)
61#define AT91_SMC_TDF GENMASK(19, 16) 61
62#define AT91_SMC_TDF_(x) ((((x) - 1) << 16) & AT91_SMC_TDF) 62#define ATMEL_HSMC_TIMINGS(cs) (0x600 + ((cs) * 0x14) + 0xc)
63#define AT91_SMC_TDF_MAX 16 63#define ATMEL_HSMC_TIMINGS_OCMS BIT(12)
64#define AT91_SMC_TDFMODE_OPTIMIZED BIT(20) 64#define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28)
65#define AT91_SMC_PMEN BIT(24) 65#define ATMEL_HSMC_TIMINGS_NFSEL BIT(31)
66#define AT91_SMC_PS GENMASK(29, 28) 66#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0
67#define AT91_SMC_PS_4 (0 << 28) 67#define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4
68#define AT91_SMC_PS_8 (1 << 28) 68#define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8
69#define AT91_SMC_PS_16 (2 << 28) 69#define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16
70#define AT91_SMC_PS_32 (3 << 28) 70#define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24
71 71
72 72/**
73/* 73 * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
74 * This function converts a setup timing expressed in nanoseconds into an 74 * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200)
75 * encoded value that can be written in the SMC_SETUP register. 75 * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200)
76 * 76 * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200)
77 * The following formula is described in atmel datasheets (section 77 * @timings: advanced NAND related timings (only applicable to HSMC)
78 * "SMC Setup Register"): 78 * @mode: all kind of config parameters (see the fields definition above).
79 * 79 * The mode fields are different on at91rm9200
80 * setup length = (128* SETUP[5] + SETUP[4:0])
81 *
82 * where setup length is the timing expressed in cycles.
83 */
84static inline u32 at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate,
85 u32 timing_ns)
86{
87 u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
88 u32 coded_cycles = 0;
89 u32 cycles;
90
91 cycles = DIV_ROUND_UP(timing_ns, clk_period);
92 if (cycles / 32) {
93 coded_cycles |= 1 << 5;
94 if (cycles < 128)
95 cycles = 0;
96 }
97
98 coded_cycles |= cycles % 32;
99
100 return coded_cycles;
101}
102
103/*
104 * This function converts a pulse timing expressed in nanoseconds into an
105 * encoded value that can be written in the SMC_PULSE register.
106 *
107 * The following formula is described in atmel datasheets (section
108 * "SMC Pulse Register"):
109 *
110 * pulse length = (256* PULSE[6] + PULSE[5:0])
111 *
112 * where pulse length is the timing expressed in cycles.
113 */ 80 */
114static inline u32 at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate, 81struct atmel_smc_cs_conf {
115 u32 timing_ns) 82 u32 setup;
116{ 83 u32 pulse;
117 u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate); 84 u32 cycle;
118 u32 coded_cycles = 0; 85 u32 timings;
119 u32 cycles; 86 u32 mode;
120 87};
121 cycles = DIV_ROUND_UP(timing_ns, clk_period); 88
122 if (cycles / 64) { 89void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
123 coded_cycles |= 1 << 6; 90int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
124 if (cycles < 256) 91 unsigned int shift,
125 cycles = 0; 92 unsigned int ncycles);
126 } 93int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
127 94 unsigned int shift, unsigned int ncycles);
128 coded_cycles |= cycles % 64; 95int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
129 96 unsigned int shift, unsigned int ncycles);
130 return coded_cycles; 97int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
131} 98 unsigned int shift, unsigned int ncycles);
132 99void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
133/* 100 const struct atmel_smc_cs_conf *conf);
134 * This function converts a cycle timing expressed in nanoseconds into an 101void atmel_hsmc_cs_conf_apply(struct regmap *regmap, int cs,
135 * encoded value that can be written in the SMC_CYCLE register. 102 const struct atmel_smc_cs_conf *conf);
136 * 103void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
137 * The following formula is described in atmel datasheets (section 104 struct atmel_smc_cs_conf *conf);
138 * "SMC Cycle Register"): 105void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs,
139 * 106 struct atmel_smc_cs_conf *conf);
140 * cycle length = (CYCLE[8:7]*256 + CYCLE[6:0])
141 *
142 * where cycle length is the timing expressed in cycles.
143 */
144static inline u32 at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate,
145 u32 timing_ns)
146{
147 u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
148 u32 coded_cycles = 0;
149 u32 cycles;
150
151 cycles = DIV_ROUND_UP(timing_ns, clk_period);
152 if (cycles / 128) {
153 coded_cycles = cycles / 256;
154 cycles %= 256;
155 if (cycles >= 128) {
156 coded_cycles++;
157 cycles = 0;
158 }
159
160 if (coded_cycles > 0x3) {
161 coded_cycles = 0x3;
162 cycles = 0x7f;
163 }
164
165 coded_cycles <<= 7;
166 }
167
168 coded_cycles |= cycles % 128;
169
170 return coded_cycles;
171}
172 107
173#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ 108#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */
diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
index c28ff21ca4d2..0622ae86f9db 100644
--- a/include/linux/mfd/syscon/exynos5-pmu.h
+++ b/include/linux/mfd/syscon/exynos5-pmu.h
@@ -46,7 +46,4 @@
46#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) 46#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
47#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) 47#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
48 48
49#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028)
50#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR BIT(28)
51
52#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */ 49#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
diff --git a/include/linux/mfd/ti-lmu-register.h b/include/linux/mfd/ti-lmu-register.h
new file mode 100644
index 000000000000..2125c7c02818
--- /dev/null
+++ b/include/linux/mfd/ti-lmu-register.h
@@ -0,0 +1,280 @@
1/*
2 * TI LMU (Lighting Management Unit) Device Register Map
3 *
4 * Copyright 2017 Texas Instruments
5 *
6 * Author: Milo Kim <milo.kim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MFD_TI_LMU_REGISTER_H__
14#define __MFD_TI_LMU_REGISTER_H__
15
16#include <linux/bitops.h>
17
18/* LM3532 */
19#define LM3532_REG_OUTPUT_CFG 0x10
20#define LM3532_ILED1_CFG_MASK 0x03
21#define LM3532_ILED2_CFG_MASK 0x0C
22#define LM3532_ILED3_CFG_MASK 0x30
23#define LM3532_ILED1_CFG_SHIFT 0
24#define LM3532_ILED2_CFG_SHIFT 2
25#define LM3532_ILED3_CFG_SHIFT 4
26
27#define LM3532_REG_RAMPUP 0x12
28#define LM3532_REG_RAMPDN LM3532_REG_RAMPUP
29#define LM3532_RAMPUP_MASK 0x07
30#define LM3532_RAMPUP_SHIFT 0
31#define LM3532_RAMPDN_MASK 0x38
32#define LM3532_RAMPDN_SHIFT 3
33
34#define LM3532_REG_ENABLE 0x1D
35
36#define LM3532_REG_PWM_A_CFG 0x13
37#define LM3532_PWM_A_MASK 0x05 /* zone 0 */
38#define LM3532_PWM_ZONE_0 BIT(2)
39
40#define LM3532_REG_PWM_B_CFG 0x14
41#define LM3532_PWM_B_MASK 0x09 /* zone 1 */
42#define LM3532_PWM_ZONE_1 BIT(3)
43
44#define LM3532_REG_PWM_C_CFG 0x15
45#define LM3532_PWM_C_MASK 0x11 /* zone 2 */
46#define LM3532_PWM_ZONE_2 BIT(4)
47
48#define LM3532_REG_ZONE_CFG_A 0x16
49#define LM3532_REG_ZONE_CFG_B 0x18
50#define LM3532_REG_ZONE_CFG_C 0x1A
51#define LM3532_ZONE_MASK (BIT(2) | BIT(3) | BIT(4))
52#define LM3532_ZONE_0 0
53#define LM3532_ZONE_1 BIT(2)
54#define LM3532_ZONE_2 BIT(3)
55
56#define LM3532_REG_BRT_A 0x70 /* zone 0 */
57#define LM3532_REG_BRT_B 0x76 /* zone 1 */
58#define LM3532_REG_BRT_C 0x7C /* zone 2 */
59
60#define LM3532_MAX_REG 0x7E
61
62/* LM3631 */
63#define LM3631_REG_DEVCTRL 0x00
64#define LM3631_LCD_EN_MASK BIT(1)
65#define LM3631_BL_EN_MASK BIT(0)
66
67#define LM3631_REG_BRT_LSB 0x01
68#define LM3631_REG_BRT_MSB 0x02
69
70#define LM3631_REG_BL_CFG 0x06
71#define LM3631_BL_CHANNEL_MASK BIT(3)
72#define LM3631_BL_DUAL_CHANNEL 0
73#define LM3631_BL_SINGLE_CHANNEL BIT(3)
74#define LM3631_MAP_MASK BIT(5)
75#define LM3631_EXPONENTIAL_MAP 0
76
77#define LM3631_REG_BRT_MODE 0x08
78#define LM3631_MODE_MASK (BIT(1) | BIT(2) | BIT(3))
79#define LM3631_DEFAULT_MODE (BIT(1) | BIT(3))
80
81#define LM3631_REG_SLOPE 0x09
82#define LM3631_SLOPE_MASK 0xF0
83#define LM3631_SLOPE_SHIFT 4
84
85#define LM3631_REG_LDO_CTRL1 0x0A
86#define LM3631_EN_OREF_MASK BIT(0)
87#define LM3631_EN_VNEG_MASK BIT(1)
88#define LM3631_EN_VPOS_MASK BIT(2)
89
90#define LM3631_REG_LDO_CTRL2 0x0B
91#define LM3631_EN_CONT_MASK BIT(0)
92
93#define LM3631_REG_VOUT_CONT 0x0C
94#define LM3631_VOUT_CONT_MASK (BIT(6) | BIT(7))
95
96#define LM3631_REG_VOUT_BOOST 0x0C
97#define LM3631_REG_VOUT_POS 0x0D
98#define LM3631_REG_VOUT_NEG 0x0E
99#define LM3631_REG_VOUT_OREF 0x0F
100#define LM3631_VOUT_MASK 0x3F
101
102#define LM3631_REG_ENTIME_VCONT 0x0B
103#define LM3631_ENTIME_CONT_MASK 0x70
104
105#define LM3631_REG_ENTIME_VOREF 0x0F
106#define LM3631_REG_ENTIME_VPOS 0x10
107#define LM3631_REG_ENTIME_VNEG 0x11
108#define LM3631_ENTIME_MASK 0xF0
109#define LM3631_ENTIME_SHIFT 4
110
111#define LM3631_MAX_REG 0x16
112
113/* LM3632 */
114#define LM3632_REG_CONFIG1 0x02
115#define LM3632_OVP_MASK (BIT(5) | BIT(6) | BIT(7))
116#define LM3632_OVP_25V BIT(6)
117
118#define LM3632_REG_CONFIG2 0x03
119#define LM3632_SWFREQ_MASK BIT(7)
120#define LM3632_SWFREQ_1MHZ BIT(7)
121
122#define LM3632_REG_BRT_LSB 0x04
123#define LM3632_REG_BRT_MSB 0x05
124
125#define LM3632_REG_IO_CTRL 0x09
126#define LM3632_PWM_MASK BIT(6)
127#define LM3632_I2C_MODE 0
128#define LM3632_PWM_MODE BIT(6)
129
130#define LM3632_REG_ENABLE 0x0A
131#define LM3632_BL_EN_MASK BIT(0)
132#define LM3632_BL_CHANNEL_MASK (BIT(3) | BIT(4))
133#define LM3632_BL_SINGLE_CHANNEL BIT(4)
134#define LM3632_BL_DUAL_CHANNEL BIT(3)
135
136#define LM3632_REG_BIAS_CONFIG 0x0C
137#define LM3632_EXT_EN_MASK BIT(0)
138#define LM3632_EN_VNEG_MASK BIT(1)
139#define LM3632_EN_VPOS_MASK BIT(2)
140
141#define LM3632_REG_VOUT_BOOST 0x0D
142#define LM3632_REG_VOUT_POS 0x0E
143#define LM3632_REG_VOUT_NEG 0x0F
144#define LM3632_VOUT_MASK 0x3F
145
146#define LM3632_MAX_REG 0x10
147
148/* LM3633 */
149#define LM3633_REG_HVLED_OUTPUT_CFG 0x10
150#define LM3633_HVLED1_CFG_MASK BIT(0)
151#define LM3633_HVLED2_CFG_MASK BIT(1)
152#define LM3633_HVLED3_CFG_MASK BIT(2)
153#define LM3633_HVLED1_CFG_SHIFT 0
154#define LM3633_HVLED2_CFG_SHIFT 1
155#define LM3633_HVLED3_CFG_SHIFT 2
156
157#define LM3633_REG_BANK_SEL 0x11
158
159#define LM3633_REG_BL0_RAMP 0x12
160#define LM3633_REG_BL1_RAMP 0x13
161#define LM3633_BL_RAMPUP_MASK 0xF0
162#define LM3633_BL_RAMPUP_SHIFT 4
163#define LM3633_BL_RAMPDN_MASK 0x0F
164#define LM3633_BL_RAMPDN_SHIFT 0
165
166#define LM3633_REG_BL_RAMP_CONF 0x1B
167#define LM3633_BL_RAMP_MASK 0x0F
168#define LM3633_BL_RAMP_EACH 0x05
169
170#define LM3633_REG_PTN0_RAMP 0x1C
171#define LM3633_REG_PTN1_RAMP 0x1D
172#define LM3633_PTN_RAMPUP_MASK 0x70
173#define LM3633_PTN_RAMPUP_SHIFT 4
174#define LM3633_PTN_RAMPDN_MASK 0x07
175#define LM3633_PTN_RAMPDN_SHIFT 0
176
177#define LM3633_REG_LED_MAPPING_MODE 0x1F
178#define LM3633_LED_EXPONENTIAL BIT(1)
179
180#define LM3633_REG_IMAX_HVLED_A 0x20
181#define LM3633_REG_IMAX_HVLED_B 0x21
182#define LM3633_REG_IMAX_LVLED_BASE 0x22
183
184#define LM3633_REG_BL_FEEDBACK_ENABLE 0x28
185
186#define LM3633_REG_ENABLE 0x2B
187#define LM3633_LED_BANK_OFFSET 2
188
189#define LM3633_REG_PATTERN 0x2C
190
191#define LM3633_REG_BOOST_CFG 0x2D
192#define LM3633_OVP_MASK (BIT(1) | BIT(2))
193#define LM3633_OVP_40V 0x6
194
195#define LM3633_REG_PWM_CFG 0x2F
196#define LM3633_PWM_A_MASK BIT(0)
197#define LM3633_PWM_B_MASK BIT(1)
198
199#define LM3633_REG_BRT_HVLED_A_LSB 0x40
200#define LM3633_REG_BRT_HVLED_A_MSB 0x41
201#define LM3633_REG_BRT_HVLED_B_LSB 0x42
202#define LM3633_REG_BRT_HVLED_B_MSB 0x43
203
204#define LM3633_REG_BRT_LVLED_BASE 0x44
205
206#define LM3633_REG_PTN_DELAY 0x50
207
208#define LM3633_REG_PTN_LOWTIME 0x51
209
210#define LM3633_REG_PTN_HIGHTIME 0x52
211
212#define LM3633_REG_PTN_LOWBRT 0x53
213
214#define LM3633_REG_PTN_HIGHBRT LM3633_REG_BRT_LVLED_BASE
215
216#define LM3633_REG_BL_OPEN_FAULT_STATUS 0xB0
217
218#define LM3633_REG_BL_SHORT_FAULT_STATUS 0xB2
219
220#define LM3633_REG_MONITOR_ENABLE 0xB4
221
222#define LM3633_MAX_REG 0xB4
223
224/* LM3695 */
225#define LM3695_REG_GP 0x10
226#define LM3695_BL_CHANNEL_MASK BIT(3)
227#define LM3695_BL_DUAL_CHANNEL 0
228#define LM3695_BL_SINGLE_CHANNEL BIT(3)
229#define LM3695_BRT_RW_MASK BIT(2)
230#define LM3695_BL_EN_MASK BIT(0)
231
232#define LM3695_REG_BRT_LSB 0x13
233#define LM3695_REG_BRT_MSB 0x14
234
235#define LM3695_MAX_REG 0x14
236
237/* LM3697 */
238#define LM3697_REG_HVLED_OUTPUT_CFG 0x10
239#define LM3697_HVLED1_CFG_MASK BIT(0)
240#define LM3697_HVLED2_CFG_MASK BIT(1)
241#define LM3697_HVLED3_CFG_MASK BIT(2)
242#define LM3697_HVLED1_CFG_SHIFT 0
243#define LM3697_HVLED2_CFG_SHIFT 1
244#define LM3697_HVLED3_CFG_SHIFT 2
245
246#define LM3697_REG_BL0_RAMP 0x11
247#define LM3697_REG_BL1_RAMP 0x12
248#define LM3697_RAMPUP_MASK 0xF0
249#define LM3697_RAMPUP_SHIFT 4
250#define LM3697_RAMPDN_MASK 0x0F
251#define LM3697_RAMPDN_SHIFT 0
252
253#define LM3697_REG_RAMP_CONF 0x14
254#define LM3697_RAMP_MASK 0x0F
255#define LM3697_RAMP_EACH 0x05
256
257#define LM3697_REG_PWM_CFG 0x1C
258#define LM3697_PWM_A_MASK BIT(0)
259#define LM3697_PWM_B_MASK BIT(1)
260
261#define LM3697_REG_IMAX_A 0x17
262#define LM3697_REG_IMAX_B 0x18
263
264#define LM3697_REG_FEEDBACK_ENABLE 0x19
265
266#define LM3697_REG_BRT_A_LSB 0x20
267#define LM3697_REG_BRT_A_MSB 0x21
268#define LM3697_REG_BRT_B_LSB 0x22
269#define LM3697_REG_BRT_B_MSB 0x23
270
271#define LM3697_REG_ENABLE 0x24
272
273#define LM3697_REG_OPEN_FAULT_STATUS 0xB0
274
275#define LM3697_REG_SHORT_FAULT_STATUS 0xB2
276
277#define LM3697_REG_MONITOR_ENABLE 0xB4
278
279#define LM3697_MAX_REG 0xB4
280#endif
diff --git a/include/linux/mfd/ti-lmu.h b/include/linux/mfd/ti-lmu.h
new file mode 100644
index 000000000000..09d5f30384e5
--- /dev/null
+++ b/include/linux/mfd/ti-lmu.h
@@ -0,0 +1,87 @@
1/*
2 * TI LMU (Lighting Management Unit) Devices
3 *
4 * Copyright 2017 Texas Instruments
5 *
6 * Author: Milo Kim <milo.kim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MFD_TI_LMU_H__
14#define __MFD_TI_LMU_H__
15
16#include <linux/gpio.h>
17#include <linux/notifier.h>
18#include <linux/regmap.h>
19
20/* Notifier event */
21#define LMU_EVENT_MONITOR_DONE 0x01
22
23enum ti_lmu_id {
24 LM3532,
25 LM3631,
26 LM3632,
27 LM3633,
28 LM3695,
29 LM3697,
30 LMU_MAX_ID,
31};
32
33enum ti_lmu_max_current {
34 LMU_IMAX_5mA,
35 LMU_IMAX_6mA,
36 LMU_IMAX_7mA = 0x03,
37 LMU_IMAX_8mA,
38 LMU_IMAX_9mA,
39 LMU_IMAX_10mA = 0x07,
40 LMU_IMAX_11mA,
41 LMU_IMAX_12mA,
42 LMU_IMAX_13mA,
43 LMU_IMAX_14mA,
44 LMU_IMAX_15mA = 0x0D,
45 LMU_IMAX_16mA,
46 LMU_IMAX_17mA,
47 LMU_IMAX_18mA,
48 LMU_IMAX_19mA,
49 LMU_IMAX_20mA = 0x13,
50 LMU_IMAX_21mA,
51 LMU_IMAX_22mA,
52 LMU_IMAX_23mA = 0x17,
53 LMU_IMAX_24mA,
54 LMU_IMAX_25mA,
55 LMU_IMAX_26mA,
56 LMU_IMAX_27mA = 0x1C,
57 LMU_IMAX_28mA,
58 LMU_IMAX_29mA,
59 LMU_IMAX_30mA,
60};
61
62enum lm363x_regulator_id {
63 LM3631_BOOST, /* Boost output */
64 LM3631_LDO_CONT, /* Display panel controller */
65 LM3631_LDO_OREF, /* Gamma reference */
66 LM3631_LDO_POS, /* Positive display bias output */
67 LM3631_LDO_NEG, /* Negative display bias output */
68 LM3632_BOOST, /* Boost output */
69 LM3632_LDO_POS, /* Positive display bias output */
70 LM3632_LDO_NEG, /* Negative display bias output */
71};
72
73/**
74 * struct ti_lmu
75 *
76 * @dev: Parent device pointer
77 * @regmap: Used for i2c communcation on accessing registers
78 * @en_gpio: GPIO for HWEN pin [Optional]
79 * @notifier: Notifier for reporting hwmon event
80 */
81struct ti_lmu {
82 struct device *dev;
83 struct regmap *regmap;
84 int en_gpio;
85 struct blocking_notifier_head notifier;
86};
87#endif
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 76c22648436f..b49fa67612f1 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -21,6 +21,8 @@
21#include <linux/list.h> 21#include <linux/list.h>
22#include <linux/regmap.h> 22#include <linux/regmap.h>
23#include <linux/mfd/wm831x/auxadc.h> 23#include <linux/mfd/wm831x/auxadc.h>
24#include <linux/mfd/wm831x/pdata.h>
25#include <linux/of.h>
24 26
25/* 27/*
26 * Register values. 28 * Register values.
@@ -367,6 +369,9 @@ struct wm831x {
367 369
368 struct regmap *regmap; 370 struct regmap *regmap;
369 371
372 struct wm831x_pdata pdata;
373 enum wm831x_parent type;
374
370 int irq; /* Our chip IRQ */ 375 int irq; /* Our chip IRQ */
371 struct mutex irq_lock; 376 struct mutex irq_lock;
372 struct irq_domain *irq_domain; 377 struct irq_domain *irq_domain;
@@ -412,7 +417,7 @@ int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
412int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, 417int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
413 int count, u16 *buf); 418 int count, u16 *buf);
414 419
415int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq); 420int wm831x_device_init(struct wm831x *wm831x, int irq);
416void wm831x_device_exit(struct wm831x *wm831x); 421void wm831x_device_exit(struct wm831x *wm831x);
417int wm831x_device_suspend(struct wm831x *wm831x); 422int wm831x_device_suspend(struct wm831x *wm831x);
418void wm831x_device_shutdown(struct wm831x *wm831x); 423void wm831x_device_shutdown(struct wm831x *wm831x);
@@ -427,4 +432,6 @@ static inline int wm831x_irq(struct wm831x *wm831x, int irq)
427 432
428extern struct regmap_config wm831x_regmap_config; 433extern struct regmap_config wm831x_regmap_config;
429 434
435extern const struct of_device_id wm831x_of_match[];
436
430#endif 437#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-22 19:11:25 -0500