aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/mfd
diff options
context:
space:
mode:
authorTony Xie <tony.xie@rock-chips.com>2019-06-21 06:32:54 -0400
committerLee Jones <lee.jones@linaro.org>2019-06-27 09:57:24 -0400
commit586c1b4125b3c7bf5b482fcafab5d568b8a3c285 (patch)
tree395407be1ea7cefbc2a417c27a63531fb22de18e /include/linux/mfd
parenta188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff)
mfd: rk808: Add RK817 and RK809 support
The RK809 and RK817 are a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators - RTC - Clocking Both RK809 and RK817 chips are using a similar register map, so we can reuse the RTC and Clocking functionality. Most of regulators have a some implementation also. Signed-off-by: Tony Xie <tony.xie@rock-chips.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/rk808.h172
1 files changed, 172 insertions, 0 deletions
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index d3156594674c..0fd9eedf3c20 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -382,6 +382,7 @@ enum rk805_reg {
382#define SWITCH1_EN BIT(5) 382#define SWITCH1_EN BIT(5)
383#define DEV_OFF_RST BIT(3) 383#define DEV_OFF_RST BIT(3)
384#define DEV_OFF BIT(0) 384#define DEV_OFF BIT(0)
385#define RTC_STOP BIT(0)
385 386
386#define VB_LO_ACT BIT(4) 387#define VB_LO_ACT BIT(4)
387#define VB_LO_SEL_3500MV (7 << 0) 388#define VB_LO_SEL_3500MV (7 << 0)
@@ -396,6 +397,175 @@ enum rk805_reg {
396#define SLEEP_FUN (0x1 << 2) 397#define SLEEP_FUN (0x1 << 2)
397#define RK8XX_ID_MSK 0xfff0 398#define RK8XX_ID_MSK 0xfff0
398#define FPWM_MODE BIT(7) 399#define FPWM_MODE BIT(7)
400enum rk817_reg_id {
401 RK817_ID_DCDC1 = 0,
402 RK817_ID_DCDC2,
403 RK817_ID_DCDC3,
404 RK817_ID_DCDC4,
405 RK817_ID_LDO1,
406 RK817_ID_LDO2,
407 RK817_ID_LDO3,
408 RK817_ID_LDO4,
409 RK817_ID_LDO5,
410 RK817_ID_LDO6,
411 RK817_ID_LDO7,
412 RK817_ID_LDO8,
413 RK817_ID_LDO9,
414 RK817_ID_BOOST,
415 RK817_ID_BOOST_OTG_SW,
416 RK817_NUM_REGULATORS
417};
418
419enum rk809_reg_id {
420 RK809_ID_DCDC5 = RK817_ID_BOOST,
421 RK809_ID_SW1,
422 RK809_ID_SW2,
423 RK809_NUM_REGULATORS
424};
425
426#define RK817_SECONDS_REG 0x00
427#define RK817_MINUTES_REG 0x01
428#define RK817_HOURS_REG 0x02
429#define RK817_DAYS_REG 0x03
430#define RK817_MONTHS_REG 0x04
431#define RK817_YEARS_REG 0x05
432#define RK817_WEEKS_REG 0x06
433#define RK817_ALARM_SECONDS_REG 0x07
434#define RK817_ALARM_MINUTES_REG 0x08
435#define RK817_ALARM_HOURS_REG 0x09
436#define RK817_ALARM_DAYS_REG 0x0a
437#define RK817_ALARM_MONTHS_REG 0x0b
438#define RK817_ALARM_YEARS_REG 0x0c
439#define RK817_RTC_CTRL_REG 0xd
440#define RK817_RTC_STATUS_REG 0xe
441#define RK817_RTC_INT_REG 0xf
442#define RK817_RTC_COMP_LSB_REG 0x10
443#define RK817_RTC_COMP_MSB_REG 0x11
444
445#define RK817_POWER_EN_REG(i) (0xb1 + (i))
446#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i))
447
448#define RK817_POWER_CONFIG (0xb9)
449
450#define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3)
451
452#define RK817_BUCK1_ON_VSEL_REG 0xBB
453#define RK817_BUCK1_SLP_VSEL_REG 0xBC
454
455#define RK817_BUCK2_CONFIG_REG 0xBD
456#define RK817_BUCK2_ON_VSEL_REG 0xBE
457#define RK817_BUCK2_SLP_VSEL_REG 0xBF
458
459#define RK817_BUCK3_CONFIG_REG 0xC0
460#define RK817_BUCK3_ON_VSEL_REG 0xC1
461#define RK817_BUCK3_SLP_VSEL_REG 0xC2
462
463#define RK817_BUCK4_CONFIG_REG 0xC3
464#define RK817_BUCK4_ON_VSEL_REG 0xC4
465#define RK817_BUCK4_SLP_VSEL_REG 0xC5
466
467#define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2)
468#define RK817_BOOST_OTG_CFG (0xde)
469
470#define RK817_ID_MSB 0xed
471#define RK817_ID_LSB 0xee
472
473#define RK817_SYS_STS 0xf0
474#define RK817_SYS_CFG(i) (0xf1 + (i))
475
476#define RK817_ON_SOURCE_REG 0xf5
477#define RK817_OFF_SOURCE_REG 0xf6
478
479/* INTERRUPT REGISTER */
480#define RK817_INT_STS_REG0 0xf8
481#define RK817_INT_STS_MSK_REG0 0xf9
482#define RK817_INT_STS_REG1 0xfa
483#define RK817_INT_STS_MSK_REG1 0xfb
484#define RK817_INT_STS_REG2 0xfc
485#define RK817_INT_STS_MSK_REG2 0xfd
486#define RK817_GPIO_INT_CFG 0xfe
487
488/* IRQ Definitions */
489#define RK817_IRQ_PWRON_FALL 0
490#define RK817_IRQ_PWRON_RISE 1
491#define RK817_IRQ_PWRON 2
492#define RK817_IRQ_PWMON_LP 3
493#define RK817_IRQ_HOTDIE 4
494#define RK817_IRQ_RTC_ALARM 5
495#define RK817_IRQ_RTC_PERIOD 6
496#define RK817_IRQ_VB_LO 7
497#define RK817_IRQ_PLUG_IN 8
498#define RK817_IRQ_PLUG_OUT 9
499#define RK817_IRQ_CHRG_TERM 10
500#define RK817_IRQ_CHRG_TIME 11
501#define RK817_IRQ_CHRG_TS 12
502#define RK817_IRQ_USB_OV 13
503#define RK817_IRQ_CHRG_IN_CLMP 14
504#define RK817_IRQ_BAT_DIS_ILIM 15
505#define RK817_IRQ_GATE_GPIO 16
506#define RK817_IRQ_TS_GPIO 17
507#define RK817_IRQ_CODEC_PD 18
508#define RK817_IRQ_CODEC_PO 19
509#define RK817_IRQ_CLASSD_MUTE_DONE 20
510#define RK817_IRQ_CLASSD_OCP 21
511#define RK817_IRQ_BAT_OVP 22
512#define RK817_IRQ_CHRG_BAT_HI 23
513#define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1)
514
515/*
516 * rtc_ctrl 0xd
517 * same as 808, except bit4
518 */
519#define RK817_RTC_CTRL_RSV4 BIT(4)
520
521/* power config 0xb9 */
522#define RK817_BUCK3_FB_RES_MSK BIT(6)
523#define RK817_BUCK3_FB_RES_INTER BIT(6)
524#define RK817_BUCK3_FB_RES_EXT 0
525
526/* buck config 0xba */
527#define RK817_RAMP_RATE_OFFSET 6
528#define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
529#define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
530#define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
531#define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
532#define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
533
534/* sys_cfg1 0xf2 */
535#define RK817_HOTDIE_TEMP_MSK (0x3 << 4)
536#define RK817_HOTDIE_85 (0x0 << 4)
537#define RK817_HOTDIE_95 (0x1 << 4)
538#define RK817_HOTDIE_105 (0x2 << 4)
539#define RK817_HOTDIE_115 (0x3 << 4)
540
541#define RK817_TSD_TEMP_MSK BIT(6)
542#define RK817_TSD_140 0
543#define RK817_TSD_160 BIT(6)
544
545#define RK817_CLK32KOUT2_EN BIT(7)
546
547/* sys_cfg3 0xf4 */
548#define RK817_SLPPIN_FUNC_MSK (0x3 << 3)
549#define SLPPIN_NULL_FUN (0x0 << 3)
550#define SLPPIN_SLP_FUN (0x1 << 3)
551#define SLPPIN_DN_FUN (0x2 << 3)
552#define SLPPIN_RST_FUN (0x3 << 3)
553
554#define RK817_RST_FUNC_MSK (0x3 << 6)
555#define RK817_RST_FUNC_SFT (6)
556#define RK817_RST_FUNC_CNT (3)
557#define RK817_RST_FUNC_DEV (0) /* reset the dev */
558#define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */
559
560#define RK817_SLPPOL_MSK BIT(5)
561#define RK817_SLPPOL_H BIT(5)
562#define RK817_SLPPOL_L (0)
563
564/* gpio&int 0xfe */
565#define RK817_INT_POL_MSK BIT(1)
566#define RK817_INT_POL_H BIT(1)
567#define RK817_INT_POL_L 0
568#define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1)
399 569
400enum { 570enum {
401 BUCK_ILMIN_50MA, 571 BUCK_ILMIN_50MA,
@@ -443,6 +613,8 @@ enum {
443enum { 613enum {
444 RK805_ID = 0x8050, 614 RK805_ID = 0x8050,
445 RK808_ID = 0x0000, 615 RK808_ID = 0x0000,
616 RK809_ID = 0x8090,
617 RK817_ID = 0x8170,
446 RK818_ID = 0x8181, 618 RK818_ID = 0x8181,
447}; 619};
448 620