diff options
| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2017-03-16 04:30:31 -0400 |
|---|---|---|
| committer | Lee Jones <lee.jones@linaro.org> | 2017-04-27 04:25:06 -0400 |
| commit | 0d69080d9e01d5d60f1887def2080ce3f66f5856 (patch) | |
| tree | 48677abc3be1fc325bb2baa686d82ec4f373fdec /include/linux/mfd | |
| parent | d9f81dad161f3f0b339a65e0e6ac5db898119027 (diff) | |
mfd: syscon: atmel-smc: Remove unused helpers/macros
All macros prefixed with AT91[SAM9]_SMC have been replaced by equivalent
definitions prefixed with ATMEL_SMC, and the at91sam9_smc_xxxx() helpers
are no longer used.
Drop these definitions before someone starts using them again.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/syscon/atmel-smc.h | 152 |
1 files changed, 0 insertions, 152 deletions
diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h index 00e6e3c8ee6f..afa266169800 100644 --- a/include/linux/mfd/syscon/atmel-smc.h +++ b/include/linux/mfd/syscon/atmel-smc.h | |||
| @@ -17,58 +17,6 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/regmap.h> | 18 | #include <linux/regmap.h> |
| 19 | 19 | ||
| 20 | #define AT91SAM9_SMC_GENERIC 0x00 | ||
| 21 | #define AT91SAM9_SMC_GENERIC_BLK_SZ 0x10 | ||
| 22 | |||
| 23 | #define SAMA5_SMC_GENERIC 0x600 | ||
| 24 | #define SAMA5_SMC_GENERIC_BLK_SZ 0x14 | ||
| 25 | |||
| 26 | #define AT91SAM9_SMC_SETUP(o) ((o) + 0x00) | ||
| 27 | #define AT91SAM9_SMC_NWESETUP(x) (x) | ||
| 28 | #define AT91SAM9_SMC_NCS_WRSETUP(x) ((x) << 8) | ||
| 29 | #define AT91SAM9_SMC_NRDSETUP(x) ((x) << 16) | ||
| 30 | #define AT91SAM9_SMC_NCS_NRDSETUP(x) ((x) << 24) | ||
| 31 | |||
| 32 | #define AT91SAM9_SMC_PULSE(o) ((o) + 0x04) | ||
| 33 | #define AT91SAM9_SMC_NWEPULSE(x) (x) | ||
| 34 | #define AT91SAM9_SMC_NCS_WRPULSE(x) ((x) << 8) | ||
| 35 | #define AT91SAM9_SMC_NRDPULSE(x) ((x) << 16) | ||
| 36 | #define AT91SAM9_SMC_NCS_NRDPULSE(x) ((x) << 24) | ||
| 37 | |||
| 38 | #define AT91SAM9_SMC_CYCLE(o) ((o) + 0x08) | ||
| 39 | #define AT91SAM9_SMC_NWECYCLE(x) (x) | ||
| 40 | #define AT91SAM9_SMC_NRDCYCLE(x) ((x) << 16) | ||
| 41 | |||
| 42 | #define AT91SAM9_SMC_MODE(o) ((o) + 0x0c) | ||
| 43 | #define SAMA5_SMC_MODE(o) ((o) + 0x10) | ||
| 44 | #define AT91_SMC_READMODE BIT(0) | ||
| 45 | #define AT91_SMC_READMODE_NCS (0 << 0) | ||
| 46 | #define AT91_SMC_READMODE_NRD (1 << 0) | ||
| 47 | #define AT91_SMC_WRITEMODE BIT(1) | ||
| 48 | #define AT91_SMC_WRITEMODE_NCS (0 << 1) | ||
| 49 | #define AT91_SMC_WRITEMODE_NWE (1 << 1) | ||
| 50 | #define AT91_SMC_EXNWMODE GENMASK(5, 4) | ||
| 51 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
| 52 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
| 53 | #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
| 54 | #define AT91_SMC_BAT BIT(8) | ||
| 55 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| 56 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| 57 | #define AT91_SMC_DBW GENMASK(13, 12) | ||
| 58 | #define AT91_SMC_DBW_8 (0 << 12) | ||
| 59 | #define AT91_SMC_DBW_16 (1 << 12) | ||
| 60 | #define AT91_SMC_DBW_32 (2 << 12) | ||
| 61 | #define AT91_SMC_TDF GENMASK(19, 16) | ||
| 62 | #define AT91_SMC_TDF_(x) ((((x) - 1) << 16) & AT91_SMC_TDF) | ||
| 63 | #define AT91_SMC_TDF_MAX 16 | ||
| 64 | #define AT91_SMC_TDFMODE_OPTIMIZED BIT(20) | ||
| 65 | #define AT91_SMC_PMEN BIT(24) | ||
| 66 | #define AT91_SMC_PS GENMASK(29, 28) | ||
| 67 | #define AT91_SMC_PS_4 (0 << 28) | ||
| 68 | #define AT91_SMC_PS_8 (1 << 28) | ||
| 69 | #define AT91_SMC_PS_16 (2 << 28) | ||
| 70 | #define AT91_SMC_PS_32 (3 << 28) | ||
| 71 | |||
| 72 | #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) | 20 | #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) |
| 73 | #define ATMEL_HSMC_SETUP(cs) (0x600 + ((cs) * 0x14)) | 21 | #define ATMEL_HSMC_SETUP(cs) (0x600 + ((cs) * 0x14)) |
| 74 | #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) | 22 | #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) |
| @@ -157,104 +105,4 @@ void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, | |||
| 157 | void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs, | 105 | void atmel_hsmc_cs_conf_get(struct regmap *regmap, int cs, |
| 158 | struct atmel_smc_cs_conf *conf); | 106 | struct atmel_smc_cs_conf *conf); |
| 159 | 107 | ||
| 160 | /* | ||
| 161 | * This function converts a setup timing expressed in nanoseconds into an | ||
| 162 | * encoded value that can be written in the SMC_SETUP register. | ||
| 163 | * | ||
| 164 | * The following formula is described in atmel datasheets (section | ||
| 165 | * "SMC Setup Register"): | ||
| 166 | * | ||
| 167 | * setup length = (128* SETUP[5] + SETUP[4:0]) | ||
| 168 | * | ||
| 169 | * where setup length is the timing expressed in cycles. | ||
| 170 | */ | ||
| 171 | static inline u32 at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate, | ||
| 172 | u32 timing_ns) | ||
| 173 | { | ||
| 174 | u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate); | ||
| 175 | u32 coded_cycles = 0; | ||
| 176 | u32 cycles; | ||
| 177 | |||
| 178 | cycles = DIV_ROUND_UP(timing_ns, clk_period); | ||
| 179 | if (cycles / 32) { | ||
| 180 | coded_cycles |= 1 << 5; | ||
| 181 | if (cycles < 128) | ||
| 182 | cycles = 0; | ||
| 183 | } | ||
| 184 | |||
| 185 | coded_cycles |= cycles % 32; | ||
| 186 | |||
| 187 | return coded_cycles; | ||
| 188 | } | ||
| 189 | |||
| 190 | /* | ||
| 191 | * This function converts a pulse timing expressed in nanoseconds into an | ||
| 192 | * encoded value that can be written in the SMC_PULSE register. | ||
| 193 | * | ||
| 194 | * The following formula is described in atmel datasheets (section | ||
| 195 | * "SMC Pulse Register"): | ||
| 196 | * | ||
| 197 | * pulse length = (256* PULSE[6] + PULSE[5:0]) | ||
| 198 | * | ||
| 199 | * where pulse length is the timing expressed in cycles. | ||
| 200 | */ | ||
| 201 | static inline u32 at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate, | ||
| 202 | u32 timing_ns) | ||
| 203 | { | ||
| 204 | u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate); | ||
| 205 | u32 coded_cycles = 0; | ||
| 206 | u32 cycles; | ||
| 207 | |||
| 208 | cycles = DIV_ROUND_UP(timing_ns, clk_period); | ||
| 209 | if (cycles / 64) { | ||
| 210 | coded_cycles |= 1 << 6; | ||
| 211 | if (cycles < 256) | ||
| 212 | cycles = 0; | ||
| 213 | } | ||
| 214 | |||
| 215 | coded_cycles |= cycles % 64; | ||
| 216 | |||
| 217 | return coded_cycles; | ||
| 218 | } | ||
| 219 | |||
| 220 | /* | ||
| 221 | * This function converts a cycle timing expressed in nanoseconds into an | ||
| 222 | * encoded value that can be written in the SMC_CYCLE register. | ||
| 223 | * | ||
| 224 | * The following formula is described in atmel datasheets (section | ||
| 225 | * "SMC Cycle Register"): | ||
| 226 | * | ||
| 227 | * cycle length = (CYCLE[8:7]*256 + CYCLE[6:0]) | ||
| 228 | * | ||
| 229 | * where cycle length is the timing expressed in cycles. | ||
| 230 | */ | ||
| 231 | static inline u32 at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate, | ||
| 232 | u32 timing_ns) | ||
| 233 | { | ||
| 234 | u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate); | ||
| 235 | u32 coded_cycles = 0; | ||
| 236 | u32 cycles; | ||
| 237 | |||
| 238 | cycles = DIV_ROUND_UP(timing_ns, clk_period); | ||
| 239 | if (cycles / 128) { | ||
| 240 | coded_cycles = cycles / 256; | ||
| 241 | cycles %= 256; | ||
| 242 | if (cycles >= 128) { | ||
| 243 | coded_cycles++; | ||
| 244 | cycles = 0; | ||
| 245 | } | ||
| 246 | |||
| 247 | if (coded_cycles > 0x3) { | ||
| 248 | coded_cycles = 0x3; | ||
| 249 | cycles = 0x7f; | ||
| 250 | } | ||
| 251 | |||
| 252 | coded_cycles <<= 7; | ||
| 253 | } | ||
| 254 | |||
| 255 | coded_cycles |= cycles % 128; | ||
| 256 | |||
| 257 | return coded_cycles; | ||
| 258 | } | ||
| 259 | |||
| 260 | #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ | 108 | #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ |
