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authorRob Herring <robh@kernel.org>2019-02-21 15:23:25 -0500
committerRob Herring <robh@kernel.org>2019-04-12 13:52:38 -0400
commitd08d42de6432d5064045159aed060e3db9fa7807 (patch)
tree2019c00522f05dfd8df93440401a2042cd085da0 /include/linux/io-pgtable.h
parent0eb2766dd6f366d42448121c383420bb0307bcc7 (diff)
iommu: io-pgtable: Add ARM Mali midgard MMU page table format
ARM Mali midgard GPU is similar to standard 64-bit stage 1 page tables, but have a few differences. Add a new format type to represent the format. The input address size is 48-bits and the output address size is 40-bits (and possibly less?). Note that the later bifrost GPUs follow the standard 64-bit stage 1 format. The differences in the format compared to 64-bit stage 1 format are: The 3rd level page entry bits are 0x1 instead of 0x3 for page entries. The access flags are not read-only and unprivileged, but read and write. This is similar to stage 2 entries, but the memory attributes field matches stage 1 being an index. The nG bit is not set by the vendor driver. This one didn't seem to matter, but we'll keep it aligned to the vendor driver. Cc: Will Deacon <will.deacon@arm.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: iommu@lists.linux-foundation.org Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190409205427.6943-2-robh@kernel.org
Diffstat (limited to 'include/linux/io-pgtable.h')
-rw-r--r--include/linux/io-pgtable.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 47d5ae559329..76969a564831 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -12,6 +12,7 @@ enum io_pgtable_fmt {
12 ARM_64_LPAE_S1, 12 ARM_64_LPAE_S1,
13 ARM_64_LPAE_S2, 13 ARM_64_LPAE_S2,
14 ARM_V7S, 14 ARM_V7S,
15 ARM_MALI_LPAE,
15 IO_PGTABLE_NUM_FMTS, 16 IO_PGTABLE_NUM_FMTS,
16}; 17};
17 18
@@ -108,6 +109,11 @@ struct io_pgtable_cfg {
108 u32 nmrr; 109 u32 nmrr;
109 u32 prrr; 110 u32 prrr;
110 } arm_v7s_cfg; 111 } arm_v7s_cfg;
112
113 struct {
114 u64 transtab;
115 u64 memattr;
116 } arm_mali_lpae_cfg;
111 }; 117 };
112}; 118};
113 119
@@ -209,5 +215,6 @@ extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
209extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns; 215extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
210extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns; 216extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
211extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns; 217extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
218extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns;
212 219
213#endif /* __IO_PGTABLE_H */ 220#endif /* __IO_PGTABLE_H */