diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-11-07 13:15:52 -0500 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-11-08 08:10:18 -0500 |
| commit | dc7b0387ee894c115ef5ddcaaf794125d6d9058c (patch) | |
| tree | 074cc9142cac12525fef1eda6ab86aa832a2cf26 /include/linux/gpio | |
| parent | dc6bafee86897419b0908e8d1e52ef46ca0ea487 (diff) | |
gpio: Move irq_valid_mask into struct gpio_irq_chip
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'include/linux/gpio')
| -rw-r--r-- | include/linux/gpio/driver.h | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 1c3d06fe54b1..067efcd4f46d 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h | |||
| @@ -99,6 +99,21 @@ struct gpio_irq_chip { | |||
| 99 | * True if set the interrupt handling is nested. | 99 | * True if set the interrupt handling is nested. |
| 100 | */ | 100 | */ |
| 101 | bool nested; | 101 | bool nested; |
| 102 | |||
| 103 | /** | ||
| 104 | * @need_valid_mask: | ||
| 105 | * | ||
| 106 | * If set core allocates @valid_mask with all bits set to one. | ||
| 107 | */ | ||
| 108 | bool need_valid_mask; | ||
| 109 | |||
| 110 | /** | ||
| 111 | * @valid_mask: | ||
| 112 | * | ||
| 113 | * If not %NULL holds bitmask of GPIOs which are valid to be included | ||
| 114 | * in IRQ domain of the chip. | ||
| 115 | */ | ||
| 116 | unsigned long *valid_mask; | ||
| 102 | }; | 117 | }; |
| 103 | 118 | ||
| 104 | static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip) | 119 | static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip) |
| @@ -170,10 +185,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip) | |||
| 170 | * safely. | 185 | * safely. |
| 171 | * @bgpio_dir: shadowed direction register for generic GPIO to clear/set | 186 | * @bgpio_dir: shadowed direction register for generic GPIO to clear/set |
| 172 | * direction safely. | 187 | * direction safely. |
| 173 | * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all | ||
| 174 | * bits set to one | ||
| 175 | * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to | ||
| 176 | * be included in IRQ domain of the chip | ||
| 177 | * @lock_key: per GPIO IRQ chip lockdep class | 188 | * @lock_key: per GPIO IRQ chip lockdep class |
| 178 | * | 189 | * |
| 179 | * A gpio_chip can help platforms abstract various sources of GPIOs so | 190 | * A gpio_chip can help platforms abstract various sources of GPIOs so |
| @@ -244,8 +255,6 @@ struct gpio_chip { | |||
| 244 | * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib | 255 | * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib |
| 245 | * to handle IRQs for most practical cases. | 256 | * to handle IRQs for most practical cases. |
| 246 | */ | 257 | */ |
| 247 | bool irq_need_valid_mask; | ||
| 248 | unsigned long *irq_valid_mask; | ||
| 249 | struct lock_class_key *lock_key; | 258 | struct lock_class_key *lock_key; |
| 250 | 259 | ||
| 251 | /** | 260 | /** |
