diff options
author | Alan Tull <atull@kernel.org> | 2018-05-16 19:49:58 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-05-25 12:23:56 -0400 |
commit | 473f01f7e4b9fc53d44c446ad22b39070c65393f (patch) | |
tree | edaaa9171a4cd9e81313e9544ffa9bb0b1144559 /include/linux/fpga | |
parent | 9f368977b4589e2fe0b9d3a4cbaf11ff6a58ecf5 (diff) |
fpga: use SPDX
Replace GPLv2 boilerplate with SPDX in FPGA code that came from me or
from Altera.
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/fpga')
-rw-r--r-- | include/linux/fpga/altera-pr-ip-core.h | 13 | ||||
-rw-r--r-- | include/linux/fpga/fpga-mgr.h | 13 | ||||
-rw-r--r-- | include/linux/fpga/fpga-region.h | 2 |
3 files changed, 4 insertions, 24 deletions
diff --git a/include/linux/fpga/altera-pr-ip-core.h b/include/linux/fpga/altera-pr-ip-core.h index 3810a9033f49..7d4664730d60 100644 --- a/include/linux/fpga/altera-pr-ip-core.h +++ b/include/linux/fpga/altera-pr-ip-core.h | |||
@@ -1,3 +1,4 @@ | |||
1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
1 | /* | 2 | /* |
2 | * Driver for Altera Partial Reconfiguration IP Core | 3 | * Driver for Altera Partial Reconfiguration IP Core |
3 | * | 4 | * |
@@ -5,18 +6,6 @@ | |||
5 | * | 6 | * |
6 | * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation | 7 | * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation |
7 | * by Alan Tull <atull@opensource.altera.com> | 8 | * by Alan Tull <atull@opensource.altera.com> |
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms and conditions of the GNU General Public License, | ||
11 | * version 2, as published by the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
16 | * more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along with | ||
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
20 | */ | 9 | */ |
21 | 10 | ||
22 | #ifndef _ALT_PR_IP_CORE_H | 11 | #ifndef _ALT_PR_IP_CORE_H |
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 1266c1108e70..eec7c2478b0d 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h | |||
@@ -1,20 +1,9 @@ | |||
1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
1 | /* | 2 | /* |
2 | * FPGA Framework | 3 | * FPGA Framework |
3 | * | 4 | * |
4 | * Copyright (C) 2013-2016 Altera Corporation | 5 | * Copyright (C) 2013-2016 Altera Corporation |
5 | * Copyright (C) 2017 Intel Corporation | 6 | * Copyright (C) 2017 Intel Corporation |
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms and conditions of the GNU General Public License, | ||
9 | * version 2, as published by the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
14 | * more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along with | ||
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
18 | */ | 7 | */ |
19 | #ifndef _LINUX_FPGA_MGR_H | 8 | #ifndef _LINUX_FPGA_MGR_H |
20 | #define _LINUX_FPGA_MGR_H | 9 | #define _LINUX_FPGA_MGR_H |
diff --git a/include/linux/fpga/fpga-region.h b/include/linux/fpga/fpga-region.h index f2e215bd1330..d7071cddd727 100644 --- a/include/linux/fpga/fpga-region.h +++ b/include/linux/fpga/fpga-region.h | |||
@@ -1,3 +1,5 @@ | |||
1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
2 | |||
1 | #ifndef _FPGA_REGION_H | 3 | #ifndef _FPGA_REGION_H |
2 | #define _FPGA_REGION_H | 4 | #define _FPGA_REGION_H |
3 | 5 | ||