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authorTero Kristo <t-kristo@ti.com>2017-02-09 04:24:37 -0500
committerTero Kristo <t-kristo@ti.com>2017-03-08 06:06:15 -0500
commit6c0afb503937a12a8d20a805fcf263e31afa9871 (patch)
tree4e0d29a53aae87a587dc802be0697facf90703e8 /include/linux/clk
parent473adbf4e02857a6b78dfb3d9fcf752638bbadb9 (diff)
clk: ti: convert to use proper register definition for all accesses
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include/linux/clk')
-rw-r--r--include/linux/clk/ti.h46
1 files changed, 24 insertions, 22 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index affdabd0b6a1..d18da839b810 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -19,6 +19,18 @@
19#include <linux/clkdev.h> 19#include <linux/clkdev.h>
20 20
21/** 21/**
22 * struct clk_omap_reg - OMAP register declaration
23 * @offset: offset from the master IP module base address
24 * @index: index of the master IP module
25 */
26struct clk_omap_reg {
27 void __iomem *ptr;
28 u16 offset;
29 u8 index;
30 u8 flags;
31};
32
33/**
22 * struct dpll_data - DPLL registers and integration data 34 * struct dpll_data - DPLL registers and integration data
23 * @mult_div1_reg: register containing the DPLL M and N bitfields 35 * @mult_div1_reg: register containing the DPLL M and N bitfields
24 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg 36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
@@ -67,12 +79,12 @@
67 * can be placed into read-only space. 79 * can be placed into read-only space.
68 */ 80 */
69struct dpll_data { 81struct dpll_data {
70 void __iomem *mult_div1_reg; 82 struct clk_omap_reg mult_div1_reg;
71 u32 mult_mask; 83 u32 mult_mask;
72 u32 div1_mask; 84 u32 div1_mask;
73 struct clk_hw *clk_bypass; 85 struct clk_hw *clk_bypass;
74 struct clk_hw *clk_ref; 86 struct clk_hw *clk_ref;
75 void __iomem *control_reg; 87 struct clk_omap_reg control_reg;
76 u32 enable_mask; 88 u32 enable_mask;
77 unsigned long last_rounded_rate; 89 unsigned long last_rounded_rate;
78 u16 last_rounded_m; 90 u16 last_rounded_m;
@@ -84,8 +96,8 @@ struct dpll_data {
84 u16 max_divider; 96 u16 max_divider;
85 unsigned long max_rate; 97 unsigned long max_rate;
86 u8 modes; 98 u8 modes;
87 void __iomem *autoidle_reg; 99 struct clk_omap_reg autoidle_reg;
88 void __iomem *idlest_reg; 100 struct clk_omap_reg idlest_reg;
89 u32 autoidle_mask; 101 u32 autoidle_mask;
90 u32 freqsel_mask; 102 u32 freqsel_mask;
91 u32 idlest_mask; 103 u32 idlest_mask;
@@ -113,10 +125,10 @@ struct clk_hw_omap;
113 */ 125 */
114struct clk_hw_omap_ops { 126struct clk_hw_omap_ops {
115 void (*find_idlest)(struct clk_hw_omap *oclk, 127 void (*find_idlest)(struct clk_hw_omap *oclk,
116 void __iomem **idlest_reg, 128 struct clk_omap_reg *idlest_reg,
117 u8 *idlest_bit, u8 *idlest_val); 129 u8 *idlest_bit, u8 *idlest_val);
118 void (*find_companion)(struct clk_hw_omap *oclk, 130 void (*find_companion)(struct clk_hw_omap *oclk,
119 void __iomem **other_reg, 131 struct clk_omap_reg *other_reg,
120 u8 *other_bit); 132 u8 *other_bit);
121 void (*allow_idle)(struct clk_hw_omap *oclk); 133 void (*allow_idle)(struct clk_hw_omap *oclk);
122 void (*deny_idle)(struct clk_hw_omap *oclk); 134 void (*deny_idle)(struct clk_hw_omap *oclk);
@@ -139,10 +151,10 @@ struct clk_hw_omap {
139 struct list_head node; 151 struct list_head node;
140 unsigned long fixed_rate; 152 unsigned long fixed_rate;
141 u8 fixed_div; 153 u8 fixed_div;
142 void __iomem *enable_reg; 154 struct clk_omap_reg enable_reg;
143 u8 enable_bit; 155 u8 enable_bit;
144 u8 flags; 156 u8 flags;
145 void __iomem *clksel_reg; 157 struct clk_omap_reg clksel_reg;
146 struct dpll_data *dpll_data; 158 struct dpll_data *dpll_data;
147 const char *clkdm_name; 159 const char *clkdm_name;
148 struct clockdomain *clkdm; 160 struct clockdomain *clkdm;
@@ -196,16 +208,6 @@ enum {
196}; 208};
197 209
198/** 210/**
199 * struct clk_omap_reg - OMAP register declaration
200 * @offset: offset from the master IP module base address
201 * @index: index of the master IP module
202 */
203struct clk_omap_reg {
204 u16 offset;
205 u16 index;
206};
207
208/**
209 * struct ti_clk_ll_ops - low-level ops for clocks 211 * struct ti_clk_ll_ops - low-level ops for clocks
210 * @clk_readl: pointer to register read function 212 * @clk_readl: pointer to register read function
211 * @clk_writel: pointer to register write function 213 * @clk_writel: pointer to register write function
@@ -222,16 +224,16 @@ struct clk_omap_reg {
222 * operations not provided directly by clock drivers. 224 * operations not provided directly by clock drivers.
223 */ 225 */
224struct ti_clk_ll_ops { 226struct ti_clk_ll_ops {
225 u32 (*clk_readl)(void __iomem *reg); 227 u32 (*clk_readl)(const struct clk_omap_reg *reg);
226 void (*clk_writel)(u32 val, void __iomem *reg); 228 void (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
227 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); 229 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
228 int (*clkdm_clk_disable)(struct clockdomain *clkdm, 230 int (*clkdm_clk_disable)(struct clockdomain *clkdm,
229 struct clk *clk); 231 struct clk *clk);
230 struct clockdomain * (*clkdm_lookup)(const char *name); 232 struct clockdomain * (*clkdm_lookup)(const char *name);
231 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, 233 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
232 u8 idlest_shift); 234 u8 idlest_shift);
233 int (*cm_split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst, 235 int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
234 u8 *idlest_reg_id); 236 s16 *prcm_inst, u8 *idlest_reg_id);
235}; 237};
236 238
237#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 239#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)