Merge tag 'drm-for-v4.13' of git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie:
 "This is the main pull request for the drm, I think I've got one later
  driver pull for mediatek SoC driver, I'm undecided on if it needs to
  go to you yet.

  Otherwise summary below:

  Core drm:
   - Atomic add driver private objects
   - Deprecate preclose hook in modern drivers
   - MST bandwidth tracking
   - Use kvmalloc in more places
   - Add mode_valid hook for crtc/encoder/bridge
   - Reduce sync_file construction time
   - Documentation updates
   - New DRM synchronisation object support

  New drivers:
   - pl111 - pl111 CLCD display controller

  Panel:
   - Innolux P079ZCA panel driver
   - Add NL12880B20-05, NL192108AC18-02D, P320HVN03 panels
   - panel-samsung-s6e3ha2: Add s6e3hf2 panel support

  i915:
   - SKL+ watermark fixes
   - G4x/G33 reset improvements
   - DP AUX backlight improvements
   - Buffer based GuC/host communication
   - New getparam for (sub)slice infomation
   - Cannonlake and Coffeelake initial patches
   - Execbuf optimisations

  radeon/amdgpu:
   - Lots of Vega10 bug fixes
   - Preliminary raven support
   - KIQ support for compute rings
   - MEC queue management rework
   - DCE6 Audio support
   - SR-IOV improvements
   - Better radeon/amdgpu selection support

  nouveau:
   - HDMI stereoscopic support
   - Display code rework for >= GM20x GPUs

  msm:
   - GEM rework for fine-grained locking
   - Per-process pagetable work
   - HDMI fixes for Snapdragon 820.

  vc4:
   - Remove 256MB CMA limit from vc4
   - Add out-fence support
   - Add support for cygnus
   - Get/set tiling ioctls support
   - Add T-format tiling support for scanout

  zte:
   - add VGA support.

  etnaviv:
   - Thermal throttle support for newer GPUs
   - Restore userspace buffer cache performance
   - dma-buf sync fix

  stm:
   - add stm32f429 display support

  exynos:
   - Rework vblank handling
   - Fixup sw-trigger code

  sun4i:
   - V3s display engine support
   - HDMI support for older SoCs
   - Preliminary work on dual-pipeline SoCs.

  rcar-du:
   - VSP work

  imx-drm:
   - Remove counter load enable from PRE
   - Double read/write reduction flag support

  tegra:
   - Documentation for the host1x and drm driver.
   - Lots of staging ioctl fixes due to grate project work.

  omapdrm:
   - dma-buf fence support
   - TILER rotation fixes"

* tag 'drm-for-v4.13' of git://people.freedesktop.org/~airlied/linux: (1270 commits)
  drm: Remove unused drm_file parameter to drm_syncobj_replace_fence()
  drm/amd/powerplay: fix bug fail to remove sysfs when rmmod amdgpu.
  amdgpu: Set cik/si_support to 1 by default if radeon isn't built
  drm/amdgpu/gfx9: fix driver reload with KIQ
  drm/amdgpu/gfx8: fix driver reload with KIQ
  drm/amdgpu: Don't call amd_powerplay_destroy() if we don't have powerplay
  drm/ttm: Fix use-after-free in ttm_bo_clean_mm
  drm/amd/amdgpu: move get memory type function from early init to sw init
  drm/amdgpu/cgs: always set reference clock in mode_info
  drm/amdgpu: fix vblank_time when displays are off
  drm/amd/powerplay: power value format change for Vega10
  drm/amdgpu/gfx9: support the amdgpu.disable_cu option
  drm/amd/powerplay: change PPSMC_MSG_GetCurrPkgPwr for Vega10
  drm/amdgpu: Make amdgpu_cs_parser_init static (v2)
  drm/amdgpu/cs: fix a typo in a comment
  drm/amdgpu: Fix the exported always on CU bitmap
  drm/amdgpu/gfx9: gfx_v9_0_enable_gfx_static_mg_power_gating() can be static
  drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup
  drm/amd/powerplay/cz: print message if smc message fails
  drm/amdgpu: fix typo in amdgpu_debugfs_test_ib_init
  ...

2 files changed, 87 insertions, 67 deletions

diff --git a/include/linux/amba/clcd-regs.h b/include/linux/amba/clcd-regs.h
new file mode 100644
index 000000000000..516a6fda83c5
--- /dev/null
+++ b/include/linux/amba/clcd-regs.h
@@ -0,0 +1,86 @@
+/*
+ * David A Rusling
+ *
+ * Copyright (C) 2001 ARM Limited
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef AMBA_CLCD_REGS_H
+#define AMBA_CLCD_REGS_H
+
+/*
+ * CLCD Controller Internal Register addresses
+ */
+#define CLCD_TIM0               0x00000000
+#define CLCD_TIM1               0x00000004
+#define CLCD_TIM2               0x00000008
+#define CLCD_TIM3               0x0000000c
+#define CLCD_UBAS               0x00000010
+#define CLCD_LBAS               0x00000014
+
+#define CLCD_PL110_IENB         0x00000018
+#define CLCD_PL110_CNTL         0x0000001c
+#define CLCD_PL110_STAT         0x00000020
+#define CLCD_PL110_INTR         0x00000024
+#define CLCD_PL110_UCUR         0x00000028
+#define CLCD_PL110_LCUR         0x0000002C
+
+#define CLCD_PL111_CNTL         0x00000018
+#define CLCD_PL111_IENB         0x0000001c
+#define CLCD_PL111_RIS          0x00000020
+#define CLCD_PL111_MIS          0x00000024
+#define CLCD_PL111_ICR          0x00000028
+#define CLCD_PL111_UCUR         0x0000002c
+#define CLCD_PL111_LCUR         0x00000030
+
+#define CLCD_PALL               0x00000200
+#define CLCD_PALETTE            0x00000200
+
+#define TIM2_PCD_LO_MASK        GENMASK(4, 0)
+#define TIM2_PCD_LO_BITS        5
+#define TIM2_CLKSEL             (1 << 5)
+#define TIM2_IVS                (1 << 11)
+#define TIM2_IHS                (1 << 12)
+#define TIM2_IPC                (1 << 13)
+#define TIM2_IOE                (1 << 14)
+#define TIM2_BCD                (1 << 26)
+#define TIM2_PCD_HI_MASK        GENMASK(31, 27)
+#define TIM2_PCD_HI_BITS        5
+#define TIM2_PCD_HI_SHIFT       27
+
+#define CNTL_LCDEN              (1 << 0)
+#define CNTL_LCDBPP1            (0 << 1)
+#define CNTL_LCDBPP2            (1 << 1)
+#define CNTL_LCDBPP4            (2 << 1)
+#define CNTL_LCDBPP8            (3 << 1)
+#define CNTL_LCDBPP16           (4 << 1)
+#define CNTL_LCDBPP16_565       (6 << 1)
+#define CNTL_LCDBPP16_444       (7 << 1)
+#define CNTL_LCDBPP24           (5 << 1)
+#define CNTL_LCDBW              (1 << 4)
+#define CNTL_LCDTFT             (1 << 5)
+#define CNTL_LCDMONO8           (1 << 6)
+#define CNTL_LCDDUAL            (1 << 7)
+#define CNTL_BGR                (1 << 8)
+#define CNTL_BEBO               (1 << 9)
+#define CNTL_BEPO               (1 << 10)
+#define CNTL_LCDPWR             (1 << 11)
+#define CNTL_LCDVCOMP(x)        ((x) << 12)
+#define CNTL_LDMAFIFOTIME       (1 << 15)
+#define CNTL_WATERMARK          (1 << 16)
+
+/* ST Microelectronics variant bits */
+#define CNTL_ST_1XBPP_444       0x0
+#define CNTL_ST_1XBPP_5551      (1 << 17)
+#define CNTL_ST_1XBPP_565       (1 << 18)
+#define CNTL_ST_CDWID_12        0x0
+#define CNTL_ST_CDWID_16        (1 << 19)
+#define CNTL_ST_CDWID_18        (1 << 20)
+#define CNTL_ST_CDWID_24        ((1 << 19)|(1 << 20))
+#define CNTL_ST_CEAEN           (1 << 21)
+#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
+
+#endif /* AMBA_CLCD_REGS_H */
diff --git a/include/linux/amba/clcd.h b/include/linux/amba/clcd.h
index 1035879b322c..d0c3be77c18e 100644
--- a/include/linux/amba/clcd.h
+++ b/include/linux/amba/clcd.h
@@ -10,73 +10,7 @@
  * for more details.
  */
 #include <linux/fb.h>
-
-/*
- * CLCD Controller Internal Register addresses
- */
-#define CLCD_TIM0               0x00000000
-#define CLCD_TIM1               0x00000004
-#define CLCD_TIM2               0x00000008
-#define CLCD_TIM3               0x0000000c
-#define CLCD_UBAS               0x00000010
-#define CLCD_LBAS               0x00000014
-
-#define CLCD_PL110_IENB         0x00000018
-#define CLCD_PL110_CNTL         0x0000001c
-#define CLCD_PL110_STAT         0x00000020
-#define CLCD_PL110_INTR         0x00000024
-#define CLCD_PL110_UCUR         0x00000028
-#define CLCD_PL110_LCUR         0x0000002C
-
-#define CLCD_PL111_CNTL         0x00000018
-#define CLCD_PL111_IENB         0x0000001c
-#define CLCD_PL111_RIS          0x00000020
-#define CLCD_PL111_MIS          0x00000024
-#define CLCD_PL111_ICR          0x00000028
-#define CLCD_PL111_UCUR         0x0000002c
-#define CLCD_PL111_LCUR         0x00000030
-
-#define CLCD_PALL               0x00000200
-#define CLCD_PALETTE            0x00000200
-
-#define TIM2_CLKSEL             (1 << 5)
-#define TIM2_IVS                (1 << 11)
-#define TIM2_IHS                (1 << 12)
-#define TIM2_IPC                (1 << 13)
-#define TIM2_IOE                (1 << 14)
-#define TIM2_BCD                (1 << 26)
-
-#define CNTL_LCDEN              (1 << 0)
-#define CNTL_LCDBPP1            (0 << 1)
-#define CNTL_LCDBPP2            (1 << 1)
-#define CNTL_LCDBPP4            (2 << 1)
-#define CNTL_LCDBPP8            (3 << 1)
-#define CNTL_LCDBPP16           (4 << 1)
-#define CNTL_LCDBPP16_565       (6 << 1)
-#define CNTL_LCDBPP16_444       (7 << 1)
-#define CNTL_LCDBPP24           (5 << 1)
-#define CNTL_LCDBW              (1 << 4)
-#define CNTL_LCDTFT             (1 << 5)
-#define CNTL_LCDMONO8           (1 << 6)
-#define CNTL_LCDDUAL            (1 << 7)
-#define CNTL_BGR                (1 << 8)
-#define CNTL_BEBO               (1 << 9)
-#define CNTL_BEPO               (1 << 10)
-#define CNTL_LCDPWR             (1 << 11)
-#define CNTL_LCDVCOMP(x)        ((x) << 12)
-#define CNTL_LDMAFIFOTIME       (1 << 15)
-#define CNTL_WATERMARK          (1 << 16)
-
-/* ST Microelectronics variant bits */
-#define CNTL_ST_1XBPP_444       0x0
-#define CNTL_ST_1XBPP_5551      (1 << 17)
-#define CNTL_ST_1XBPP_565       (1 << 18)
-#define CNTL_ST_CDWID_12        0x0
-#define CNTL_ST_CDWID_16        (1 << 19)
-#define CNTL_ST_CDWID_18        (1 << 20)
-#define CNTL_ST_CDWID_24        ((1 << 19)|(1 << 20))
-#define CNTL_ST_CEAEN           (1 << 21)
-#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
+#include <linux/amba/clcd-regs.h>
 
 enum {
         /* individual formats */