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authorLinus Torvalds <torvalds@linux-foundation.org>2016-08-02 16:11:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-08-02 16:11:27 -0400
commit221bb8a46e230b9824204ae86537183d9991ff2a (patch)
tree92510d72285b2285be7cb87288bf088cb28af4c1 /include/kvm
parentf7b32e4c021fd788f13f6785e17efbc3eb05b351 (diff)
parent23528bb21ee2c9b27f3feddd77a2a3351a8df148 (diff)
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Paolo Bonzini: - ARM: GICv3 ITS emulation and various fixes. Removal of the old VGIC implementation. - s390: support for trapping software breakpoints, nested virtualization (vSIE), the STHYI opcode, initial extensions for CPU model support. - MIPS: support for MIPS64 hosts (32-bit guests only) and lots of cleanups, preliminary to this and the upcoming support for hardware virtualization extensions. - x86: support for execute-only mappings in nested EPT; reduced vmexit latency for TSC deadline timer (by about 30%) on Intel hosts; support for more than 255 vCPUs. - PPC: bugfixes. * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (302 commits) KVM: PPC: Introduce KVM_CAP_PPC_HTM MIPS: Select HAVE_KVM for MIPS64_R{2,6} MIPS: KVM: Reset CP0_PageMask during host TLB flush MIPS: KVM: Fix ptr->int cast via KVM_GUEST_KSEGX() MIPS: KVM: Sign extend MFC0/RDHWR results MIPS: KVM: Fix 64-bit big endian dynamic translation MIPS: KVM: Fail if ebase doesn't fit in CP0_EBase MIPS: KVM: Use 64-bit CP0_EBase when appropriate MIPS: KVM: Set CP0_Status.KX on MIPS64 MIPS: KVM: Make entry code MIPS64 friendly MIPS: KVM: Use kmap instead of CKSEG0ADDR() MIPS: KVM: Use virt_to_phys() to get commpage PFN MIPS: Fix definition of KSEGX() for 64-bit KVM: VMX: Add VMCS to CPU's loaded VMCSs before VMPTRLD kvm: x86: nVMX: maintain internal copy of current VMCS KVM: PPC: Book3S HV: Save/restore TM state in H_CEDE KVM: PPC: Book3S HV: Pull out TM state save/restore into separate procedures KVM: arm64: vgic-its: Simplify MAPI error handling KVM: arm64: vgic-its: Make vgic_its_cmd_handle_mapi similar to other handlers KVM: arm64: vgic-its: Turn device_id validation into generic ID validation ...
Diffstat (limited to 'include/kvm')
-rw-r--r--include/kvm/arm_vgic.h438
-rw-r--r--include/kvm/vgic/vgic.h246
2 files changed, 190 insertions, 494 deletions
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index da0a524802cb..540da5149ba7 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -1,6 +1,5 @@
1/* 1/*
2 * Copyright (C) 2012 ARM Ltd. 2 * Copyright (C) 2015, 2016 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 * 3 *
5 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -12,16 +11,10 @@
12 * GNU General Public License for more details. 11 * GNU General Public License for more details.
13 * 12 *
14 * You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 15 */
18 16#ifndef __KVM_ARM_VGIC_H
19#ifndef __ASM_ARM_KVM_VGIC_H 17#define __KVM_ARM_VGIC_H
20#define __ASM_ARM_KVM_VGIC_H
21
22#ifdef CONFIG_KVM_NEW_VGIC
23#include <kvm/vgic/vgic.h>
24#else
25 18
26#include <linux/kernel.h> 19#include <linux/kernel.h>
27#include <linux/kvm.h> 20#include <linux/kvm.h>
@@ -29,248 +22,187 @@
29#include <linux/spinlock.h> 22#include <linux/spinlock.h>
30#include <linux/types.h> 23#include <linux/types.h>
31#include <kvm/iodev.h> 24#include <kvm/iodev.h>
32#include <linux/irqchip/arm-gic-common.h> 25#include <linux/list.h>
33 26
34#define VGIC_NR_IRQS_LEGACY 256 27#define VGIC_V3_MAX_CPUS 255
28#define VGIC_V2_MAX_CPUS 8
29#define VGIC_NR_IRQS_LEGACY 256
35#define VGIC_NR_SGIS 16 30#define VGIC_NR_SGIS 16
36#define VGIC_NR_PPIS 16 31#define VGIC_NR_PPIS 16
37#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 32#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
34#define VGIC_MAX_SPI 1019
35#define VGIC_MAX_RESERVED 1023
36#define VGIC_MIN_LPI 8192
38 37
39#define VGIC_V2_MAX_LRS (1 << 6) 38enum vgic_type {
40#define VGIC_V3_MAX_LRS 16 39 VGIC_V2, /* Good ol' GICv2 */
41#define VGIC_MAX_IRQS 1024 40 VGIC_V3, /* New fancy GICv3 */
42#define VGIC_V2_MAX_CPUS 8 41};
43#define VGIC_V3_MAX_CPUS 255
44 42
45#if (VGIC_NR_IRQS_LEGACY & 31) 43/* same for all guests, as depending only on the _host's_ GIC model */
46#error "VGIC_NR_IRQS must be a multiple of 32" 44struct vgic_global {
47#endif 45 /* type of the host GIC */
46 enum vgic_type type;
48 47
49#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) 48 /* Physical address of vgic virtual cpu interface */
50#error "VGIC_NR_IRQS must be <= 1024" 49 phys_addr_t vcpu_base;
51#endif
52 50
53/* 51 /* virtual control interface mapping */
54 * The GIC distributor registers describing interrupts have two parts: 52 void __iomem *vctrl_base;
55 * - 32 per-CPU interrupts (SGI + PPI)
56 * - a bunch of shared interrupts (SPI)
57 */
58struct vgic_bitmap {
59 /*
60 * - One UL per VCPU for private interrupts (assumes UL is at
61 * least 32 bits)
62 * - As many UL as necessary for shared interrupts.
63 *
64 * The private interrupts are accessed via the "private"
65 * field, one UL per vcpu (the state for vcpu n is in
66 * private[n]). The shared interrupts are accessed via the
67 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
68 */
69 unsigned long *private;
70 unsigned long *shared;
71};
72 53
73struct vgic_bytemap { 54 /* Number of implemented list registers */
74 /* 55 int nr_lr;
75 * - 8 u32 per VCPU for private interrupts
76 * - As many u32 as necessary for shared interrupts.
77 *
78 * The private interrupts are accessed via the "private"
79 * field, (the state for vcpu n is in private[n*8] to
80 * private[n*8 + 7]). The shared interrupts are accessed via
81 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
82 * shared[(n-32)/4] word).
83 */
84 u32 *private;
85 u32 *shared;
86};
87 56
88struct kvm_vcpu; 57 /* Maintenance IRQ number */
58 unsigned int maint_irq;
89 59
90enum vgic_type { 60 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
91 VGIC_V2, /* Good ol' GICv2 */ 61 int max_gic_vcpus;
92 VGIC_V3, /* New fancy GICv3 */ 62
63 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
64 bool can_emulate_gicv2;
93}; 65};
94 66
95#define LR_STATE_PENDING (1 << 0) 67extern struct vgic_global kvm_vgic_global_state;
96#define LR_STATE_ACTIVE (1 << 1)
97#define LR_STATE_MASK (3 << 0)
98#define LR_EOI_INT (1 << 2)
99#define LR_HW (1 << 3)
100 68
101struct vgic_lr { 69#define VGIC_V2_MAX_LRS (1 << 6)
102 unsigned irq:10; 70#define VGIC_V3_MAX_LRS 16
103 union { 71#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
104 unsigned hwirq:10;
105 unsigned source:3;
106 };
107 unsigned state:4;
108};
109 72
110struct vgic_vmcr { 73enum vgic_irq_config {
111 u32 ctlr; 74 VGIC_CONFIG_EDGE = 0,
112 u32 abpr; 75 VGIC_CONFIG_LEVEL
113 u32 bpr;
114 u32 pmr;
115}; 76};
116 77
117struct vgic_ops { 78struct vgic_irq {
118 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); 79 spinlock_t irq_lock; /* Protects the content of the struct */
119 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); 80 struct list_head lpi_list; /* Used to link all LPIs together */
120 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); 81 struct list_head ap_list;
121 u64 (*get_eisr)(const struct kvm_vcpu *vcpu); 82
122 void (*clear_eisr)(struct kvm_vcpu *vcpu); 83 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
123 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); 84 * SPIs and LPIs: The VCPU whose ap_list
124 void (*enable_underflow)(struct kvm_vcpu *vcpu); 85 * this is queued on.
125 void (*disable_underflow)(struct kvm_vcpu *vcpu); 86 */
126 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 87
127 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 88 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
128 void (*enable)(struct kvm_vcpu *vcpu); 89 * be sent to, as a result of the
90 * targets reg (v2) or the
91 * affinity reg (v3).
92 */
93
94 u32 intid; /* Guest visible INTID */
95 bool pending;
96 bool line_level; /* Level only */
97 bool soft_pending; /* Level only */
98 bool active; /* not used for LPIs */
99 bool enabled;
100 bool hw; /* Tied to HW IRQ */
101 struct kref refcount; /* Used for LPIs */
102 u32 hwintid; /* HW INTID number */
103 union {
104 u8 targets; /* GICv2 target VCPUs mask */
105 u32 mpidr; /* GICv3 target VCPU */
106 };
107 u8 source; /* GICv2 SGIs only */
108 u8 priority;
109 enum vgic_irq_config config; /* Level or edge */
129}; 110};
130 111
131struct vgic_params { 112struct vgic_register_region;
132 /* vgic type */ 113struct vgic_its;
133 enum vgic_type type;
134 /* Physical address of vgic virtual cpu interface */
135 phys_addr_t vcpu_base;
136 /* Number of list registers */
137 u32 nr_lr;
138 /* Interrupt number */
139 unsigned int maint_irq;
140 /* Virtual control interface base address */
141 void __iomem *vctrl_base;
142 int max_gic_vcpus;
143 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
144 bool can_emulate_gicv2;
145};
146 114
147struct vgic_vm_ops { 115enum iodev_type {
148 bool (*queue_sgi)(struct kvm_vcpu *, int irq); 116 IODEV_CPUIF,
149 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); 117 IODEV_DIST,
150 int (*init_model)(struct kvm *); 118 IODEV_REDIST,
151 int (*map_resources)(struct kvm *, const struct vgic_params *); 119 IODEV_ITS
152}; 120};
153 121
154struct vgic_io_device { 122struct vgic_io_device {
155 gpa_t addr; 123 gpa_t base_addr;
156 int len; 124 union {
157 const struct vgic_io_range *reg_ranges; 125 struct kvm_vcpu *redist_vcpu;
158 struct kvm_vcpu *redist_vcpu; 126 struct vgic_its *its;
127 };
128 const struct vgic_register_region *regions;
129 enum iodev_type iodev_type;
130 int nr_regions;
159 struct kvm_io_device dev; 131 struct kvm_io_device dev;
160}; 132};
161 133
162struct irq_phys_map { 134struct vgic_its {
163 u32 virt_irq; 135 /* The base address of the ITS control register frame */
164 u32 phys_irq; 136 gpa_t vgic_its_base;
165}; 137
166 138 bool enabled;
167struct irq_phys_map_entry { 139 bool initialized;
168 struct list_head entry; 140 struct vgic_io_device iodev;
169 struct rcu_head rcu; 141 struct kvm_device *dev;
170 struct irq_phys_map map; 142
143 /* These registers correspond to GITS_BASER{0,1} */
144 u64 baser_device_table;
145 u64 baser_coll_table;
146
147 /* Protects the command queue */
148 struct mutex cmd_lock;
149 u64 cbaser;
150 u32 creadr;
151 u32 cwriter;
152
153 /* Protects the device and collection lists */
154 struct mutex its_lock;
155 struct list_head device_list;
156 struct list_head collection_list;
171}; 157};
172 158
173struct vgic_dist { 159struct vgic_dist {
174 spinlock_t lock;
175 bool in_kernel; 160 bool in_kernel;
176 bool ready; 161 bool ready;
162 bool initialized;
177 163
178 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 164 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
179 u32 vgic_model; 165 u32 vgic_model;
180 166
181 int nr_cpus; 167 /* Do injected MSIs require an additional device ID? */
182 int nr_irqs; 168 bool msis_require_devid;
169
170 int nr_spis;
183 171
172 /* TODO: Consider moving to global state */
184 /* Virtual control interface mapping */ 173 /* Virtual control interface mapping */
185 void __iomem *vctrl_base; 174 void __iomem *vctrl_base;
186 175
187 /* Distributor and vcpu interface mapping in the guest */ 176 /* base addresses in guest physical address space: */
188 phys_addr_t vgic_dist_base; 177 gpa_t vgic_dist_base; /* distributor */
189 /* GICv2 and GICv3 use different mapped register blocks */
190 union { 178 union {
191 phys_addr_t vgic_cpu_base; 179 /* either a GICv2 CPU interface */
192 phys_addr_t vgic_redist_base; 180 gpa_t vgic_cpu_base;
181 /* or a number of GICv3 redistributor regions */
182 gpa_t vgic_redist_base;
193 }; 183 };
194 184
195 /* Distributor enabled */ 185 /* distributor enabled */
196 u32 enabled; 186 bool enabled;
197
198 /* Interrupt enabled (one bit per IRQ) */
199 struct vgic_bitmap irq_enabled;
200
201 /* Level-triggered interrupt external input is asserted */
202 struct vgic_bitmap irq_level;
203
204 /*
205 * Interrupt state is pending on the distributor
206 */
207 struct vgic_bitmap irq_pending;
208
209 /*
210 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
211 * interrupts. Essentially holds the state of the flip-flop in
212 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
213 * Once set, it is only cleared for level-triggered interrupts on
214 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
215 */
216 struct vgic_bitmap irq_soft_pend;
217
218 /* Level-triggered interrupt queued on VCPU interface */
219 struct vgic_bitmap irq_queued;
220
221 /* Interrupt was active when unqueue from VCPU interface */
222 struct vgic_bitmap irq_active;
223
224 /* Interrupt priority. Not used yet. */
225 struct vgic_bytemap irq_priority;
226 187
227 /* Level/edge triggered */ 188 struct vgic_irq *spis;
228 struct vgic_bitmap irq_cfg;
229 189
230 /* 190 struct vgic_io_device dist_iodev;
231 * Source CPU per SGI and target CPU:
232 *
233 * Each byte represent a SGI observable on a VCPU, each bit of
234 * this byte indicating if the corresponding VCPU has
235 * generated this interrupt. This is a GICv2 feature only.
236 *
237 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
238 * the SGIs observable on VCPUn.
239 */
240 u8 *irq_sgi_sources;
241 191
242 /* 192 bool has_its;
243 * Target CPU for each SPI:
244 *
245 * Array of available SPI, each byte indicating the target
246 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
247 */
248 u8 *irq_spi_cpu;
249 193
250 /* 194 /*
251 * Reverse lookup of irq_spi_cpu for faster compute pending: 195 * Contains the attributes and gpa of the LPI configuration table.
252 * 196 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
253 * Array of bitmaps, one per VCPU, describing if IRQn is 197 * one address across all redistributors.
254 * routed to a particular VCPU. 198 * GICv3 spec: 6.1.2 "LPI Configuration tables"
255 */ 199 */
256 struct vgic_bitmap *irq_spi_target; 200 u64 propbaser;
257
258 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
259 u32 *irq_spi_mpidr;
260 201
261 /* Bitmap indicating which CPU has something pending */ 202 /* Protects the lpi_list and the count value below. */
262 unsigned long *irq_pending_on_cpu; 203 spinlock_t lpi_list_lock;
263 204 struct list_head lpi_list_head;
264 /* Bitmap indicating which CPU has active IRQs */ 205 int lpi_list_count;
265 unsigned long *irq_active_on_cpu;
266
267 struct vgic_vm_ops vm_ops;
268 struct vgic_io_device dist_iodev;
269 struct vgic_io_device *redist_iodevs;
270
271 /* Virtual irq to hwirq mapping */
272 spinlock_t irq_phys_map_lock;
273 struct list_head irq_phys_map_list;
274}; 206};
275 207
276struct vgic_v2_cpu_if { 208struct vgic_v2_cpu_if {
@@ -298,78 +230,88 @@ struct vgic_v3_cpu_if {
298}; 230};
299 231
300struct vgic_cpu { 232struct vgic_cpu {
301 /* Pending/active/both interrupts on this VCPU */
302 DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS);
303 DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS);
304 DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
305
306 /* Pending/active/both shared interrupts, dynamically sized */
307 unsigned long *pending_shared;
308 unsigned long *active_shared;
309 unsigned long *pend_act_shared;
310
311 /* CPU vif control registers for world switch */ 233 /* CPU vif control registers for world switch */
312 union { 234 union {
313 struct vgic_v2_cpu_if vgic_v2; 235 struct vgic_v2_cpu_if vgic_v2;
314 struct vgic_v3_cpu_if vgic_v3; 236 struct vgic_v3_cpu_if vgic_v3;
315 }; 237 };
316 238
317 /* Protected by the distributor's irq_phys_map_lock */ 239 unsigned int used_lrs;
318 struct list_head irq_phys_map_list; 240 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
319 241
320 u64 live_lrs; 242 spinlock_t ap_list_lock; /* Protects the ap_list */
321}; 243
244 /*
245 * List of IRQs that this VCPU should consider because they are either
246 * Active or Pending (hence the name; AP list), or because they recently
247 * were one of the two and need to be migrated off this list to another
248 * VCPU.
249 */
250 struct list_head ap_list_head;
322 251
323#define LR_EMPTY 0xff 252 u64 live_lrs;
324 253
325#define INT_STATUS_EOI (1 << 0) 254 /*
326#define INT_STATUS_UNDERFLOW (1 << 1) 255 * Members below are used with GICv3 emulation only and represent
256 * parts of the redistributor.
257 */
258 struct vgic_io_device rd_iodev;
259 struct vgic_io_device sgi_iodev;
327 260
328struct kvm; 261 /* Contains the attributes and gpa of the LPI pending tables. */
329struct kvm_vcpu; 262 u64 pendbaser;
263
264 bool lpis_enabled;
265};
330 266
331int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 267int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
332int kvm_vgic_hyp_init(void);
333int kvm_vgic_map_resources(struct kvm *kvm);
334int kvm_vgic_get_max_vcpus(void);
335void kvm_vgic_early_init(struct kvm *kvm); 268void kvm_vgic_early_init(struct kvm *kvm);
336int kvm_vgic_create(struct kvm *kvm, u32 type); 269int kvm_vgic_create(struct kvm *kvm, u32 type);
337void kvm_vgic_destroy(struct kvm *kvm); 270void kvm_vgic_destroy(struct kvm *kvm);
338void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 271void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
339void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 272void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
340void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 273int kvm_vgic_map_resources(struct kvm *kvm);
341void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 274int kvm_vgic_hyp_init(void);
342int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, 275
276int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
343 bool level); 277 bool level);
344int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, 278int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
345 unsigned int virt_irq, bool level); 279 bool level);
346void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 280int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
347int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
348int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, int virt_irq, int phys_irq);
349int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); 281int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
350bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); 282bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
351 283
284int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
285
352#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 286#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
353#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) 287#define vgic_initialized(k) ((k)->arch.vgic.initialized)
354#define vgic_ready(k) ((k)->arch.vgic.ready) 288#define vgic_ready(k) ((k)->arch.vgic.ready)
355#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 289#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
356 ((i) < (k)->arch.vgic.nr_irqs)) 290 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
291
292bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
293void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
294void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
357 295
358int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info,
359 const struct vgic_ops **ops,
360 const struct vgic_params **params);
361#ifdef CONFIG_KVM_ARM_VGIC_V3 296#ifdef CONFIG_KVM_ARM_VGIC_V3
362int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, 297void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
363 const struct vgic_ops **ops,
364 const struct vgic_params **params);
365#else 298#else
366static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, 299static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
367 const struct vgic_ops **ops,
368 const struct vgic_params **params)
369{ 300{
370 return -ENODEV;
371} 301}
372#endif 302#endif
373 303
374#endif /* old VGIC include */ 304/**
375#endif 305 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
306 *
307 * The host's GIC naturally limits the maximum amount of VCPUs a guest
308 * can use.
309 */
310static inline int kvm_vgic_get_max_vcpus(void)
311{
312 return kvm_vgic_global_state.max_gic_vcpus;
313}
314
315int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
316
317#endif /* __KVM_ARM_VGIC_H */
diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
deleted file mode 100644
index 3fbd175265ae..000000000000
--- a/include/kvm/vgic/vgic.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * Copyright (C) 2015, 2016 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_ARM_KVM_VGIC_VGIC_H
17#define __ASM_ARM_KVM_VGIC_VGIC_H
18
19#include <linux/kernel.h>
20#include <linux/kvm.h>
21#include <linux/irqreturn.h>
22#include <linux/spinlock.h>
23#include <linux/types.h>
24#include <kvm/iodev.h>
25
26#define VGIC_V3_MAX_CPUS 255
27#define VGIC_V2_MAX_CPUS 8
28#define VGIC_NR_IRQS_LEGACY 256
29#define VGIC_NR_SGIS 16
30#define VGIC_NR_PPIS 16
31#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
32#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
33#define VGIC_MAX_SPI 1019
34#define VGIC_MAX_RESERVED 1023
35#define VGIC_MIN_LPI 8192
36
37enum vgic_type {
38 VGIC_V2, /* Good ol' GICv2 */
39 VGIC_V3, /* New fancy GICv3 */
40};
41
42/* same for all guests, as depending only on the _host's_ GIC model */
43struct vgic_global {
44 /* type of the host GIC */
45 enum vgic_type type;
46
47 /* Physical address of vgic virtual cpu interface */
48 phys_addr_t vcpu_base;
49
50 /* virtual control interface mapping */
51 void __iomem *vctrl_base;
52
53 /* Number of implemented list registers */
54 int nr_lr;
55
56 /* Maintenance IRQ number */
57 unsigned int maint_irq;
58
59 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
60 int max_gic_vcpus;
61
62 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
63 bool can_emulate_gicv2;
64};
65
66extern struct vgic_global kvm_vgic_global_state;
67
68#define VGIC_V2_MAX_LRS (1 << 6)
69#define VGIC_V3_MAX_LRS 16
70#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
71
72enum vgic_irq_config {
73 VGIC_CONFIG_EDGE = 0,
74 VGIC_CONFIG_LEVEL
75};
76
77struct vgic_irq {
78 spinlock_t irq_lock; /* Protects the content of the struct */
79 struct list_head ap_list;
80
81 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
82 * SPIs and LPIs: The VCPU whose ap_list
83 * this is queued on.
84 */
85
86 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
87 * be sent to, as a result of the
88 * targets reg (v2) or the
89 * affinity reg (v3).
90 */
91
92 u32 intid; /* Guest visible INTID */
93 bool pending;
94 bool line_level; /* Level only */
95 bool soft_pending; /* Level only */
96 bool active; /* not used for LPIs */
97 bool enabled;
98 bool hw; /* Tied to HW IRQ */
99 u32 hwintid; /* HW INTID number */
100 union {
101 u8 targets; /* GICv2 target VCPUs mask */
102 u32 mpidr; /* GICv3 target VCPU */
103 };
104 u8 source; /* GICv2 SGIs only */
105 u8 priority;
106 enum vgic_irq_config config; /* Level or edge */
107};
108
109struct vgic_register_region;
110
111struct vgic_io_device {
112 gpa_t base_addr;
113 struct kvm_vcpu *redist_vcpu;
114 const struct vgic_register_region *regions;
115 int nr_regions;
116 struct kvm_io_device dev;
117};
118
119struct vgic_dist {
120 bool in_kernel;
121 bool ready;
122 bool initialized;
123
124 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
125 u32 vgic_model;
126
127 int nr_spis;
128
129 /* TODO: Consider moving to global state */
130 /* Virtual control interface mapping */
131 void __iomem *vctrl_base;
132
133 /* base addresses in guest physical address space: */
134 gpa_t vgic_dist_base; /* distributor */
135 union {
136 /* either a GICv2 CPU interface */
137 gpa_t vgic_cpu_base;
138 /* or a number of GICv3 redistributor regions */
139 gpa_t vgic_redist_base;
140 };
141
142 /* distributor enabled */
143 bool enabled;
144
145 struct vgic_irq *spis;
146
147 struct vgic_io_device dist_iodev;
148 struct vgic_io_device *redist_iodevs;
149};
150
151struct vgic_v2_cpu_if {
152 u32 vgic_hcr;
153 u32 vgic_vmcr;
154 u32 vgic_misr; /* Saved only */
155 u64 vgic_eisr; /* Saved only */
156 u64 vgic_elrsr; /* Saved only */
157 u32 vgic_apr;
158 u32 vgic_lr[VGIC_V2_MAX_LRS];
159};
160
161struct vgic_v3_cpu_if {
162#ifdef CONFIG_KVM_ARM_VGIC_V3
163 u32 vgic_hcr;
164 u32 vgic_vmcr;
165 u32 vgic_sre; /* Restored only, change ignored */
166 u32 vgic_misr; /* Saved only */
167 u32 vgic_eisr; /* Saved only */
168 u32 vgic_elrsr; /* Saved only */
169 u32 vgic_ap0r[4];
170 u32 vgic_ap1r[4];
171 u64 vgic_lr[VGIC_V3_MAX_LRS];
172#endif
173};
174
175struct vgic_cpu {
176 /* CPU vif control registers for world switch */
177 union {
178 struct vgic_v2_cpu_if vgic_v2;
179 struct vgic_v3_cpu_if vgic_v3;
180 };
181
182 unsigned int used_lrs;
183 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
184
185 spinlock_t ap_list_lock; /* Protects the ap_list */
186
187 /*
188 * List of IRQs that this VCPU should consider because they are either
189 * Active or Pending (hence the name; AP list), or because they recently
190 * were one of the two and need to be migrated off this list to another
191 * VCPU.
192 */
193 struct list_head ap_list_head;
194
195 u64 live_lrs;
196};
197
198int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
199void kvm_vgic_early_init(struct kvm *kvm);
200int kvm_vgic_create(struct kvm *kvm, u32 type);
201void kvm_vgic_destroy(struct kvm *kvm);
202void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
203void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
204int kvm_vgic_map_resources(struct kvm *kvm);
205int kvm_vgic_hyp_init(void);
206
207int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
208 bool level);
209int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
210 bool level);
211int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
212int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
213bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
214
215int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
216
217#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
218#define vgic_initialized(k) ((k)->arch.vgic.initialized)
219#define vgic_ready(k) ((k)->arch.vgic.ready)
220#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
221 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
222
223bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
224void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
225void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
226
227#ifdef CONFIG_KVM_ARM_VGIC_V3
228void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
229#else
230static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
231{
232}
233#endif
234
235/**
236 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
237 *
238 * The host's GIC naturally limits the maximum amount of VCPUs a guest
239 * can use.
240 */
241static inline int kvm_vgic_get_max_vcpus(void)
242{
243 return kvm_vgic_global_state.max_gic_vcpus;
244}
245
246#endif /* __ASM_ARM_KVM_VGIC_VGIC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 22:44:56 -0400