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authorLinus Torvalds <torvalds@linux-foundation.org>2016-08-01 18:36:01 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-08-01 18:36:01 -0400
commit43a0a98aa8da71583f84b84fd72e265c24d4c5f8 (patch)
tree3830aff2b36f48a67be5f485f00f56cf4269729d /include/dt-bindings/reset
parent6911a5281430cf6897376487698504620f454791 (diff)
parentf8c6d88b2c874295f49b9ad1ca0826b9a8ef3180 (diff)
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs. A slew of changes this release cycle. The reset driver tree, that we merge through arm-soc for historical reasons, is also sizable this time around. Among the changes: - clps711x: Treewide changes to compatible strings, merged here for simplicity. - Qualcomm: SCM firmware driver cleanups, move to platform driver - ux500: Major cleanups, removal of old mach-specific infrastructure. - Atmel external bus memory driver - Move of brcmstb platform to the rest of bcm - PMC driver updates for tegra, various fixes and improvements - Samsung platform driver updates to support 64-bit Exynos platforms - Reset controller cleanups moving to devm_reset_controller_register() APIs - Reset controller driver for Amlogic Meson - Reset controller driver for Hisilicon hi6220 - ARM SCPI power domain support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits) ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data soc: raspberrypi-power: add CONFIG_OF dependency firmware: scpi: add CONFIG_OF dependency video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip pwm: clps711x: Changing the compatibility string to match with the smallest supported chip serial: clps711x: Changing the compatibility string to match with the smallest supported chip irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip clk: clps711x: Changing the compatibility string to match with the smallest supported chip ...
Diffstat (limited to 'include/dt-bindings/reset')
-rw-r--r--include/dt-bindings/reset/amlogic,meson-gxbb-reset.h210
-rw-r--r--include/dt-bindings/reset/amlogic,meson8b-reset.h175
-rw-r--r--include/dt-bindings/reset/hisi,hi6220-resets.h8
-rw-r--r--include/dt-bindings/reset/ti-syscon.h38
4 files changed, 431 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
new file mode 100644
index 000000000000..524d6077ac1b
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
@@ -0,0 +1,210 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * BSD LICENSE
25 *
26 * Copyright (c) 2016 BayLibre, SAS.
27 * Author: Neil Armstrong <narmstrong@baylibre.com>
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
56#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
57
58/* RESET0 */
59#define RESET_HIU 0
60/* 1 */
61#define RESET_DOS_RESET 2
62#define RESET_DDR_TOP 3
63#define RESET_DCU_RESET 4
64#define RESET_VIU 5
65#define RESET_AIU 6
66#define RESET_VID_PLL_DIV 7
67/* 8 */
68#define RESET_PMUX 9
69#define RESET_VENC 10
70#define RESET_ASSIST 11
71#define RESET_AFIFO2 12
72#define RESET_VCBUS 13
73/* 14 */
74/* 15 */
75#define RESET_GIC 16
76#define RESET_CAPB3_DECODE 17
77#define RESET_NAND_CAPB3 18
78#define RESET_HDMITX_CAPB3 19
79#define RESET_MALI_CAPB3 20
80#define RESET_DOS_CAPB3 21
81#define RESET_SYS_CPU_CAPB3 22
82#define RESET_CBUS_CAPB3 23
83#define RESET_AHB_CNTL 24
84#define RESET_AHB_DATA 25
85#define RESET_VCBUS_CLK81 26
86#define RESET_MMC 27
87#define RESET_MIPI_0 28
88#define RESET_MIPI_1 29
89#define RESET_MIPI_2 30
90#define RESET_MIPI_3 31
91/* RESET1 */
92#define RESET_CPPM 32
93#define RESET_DEMUX 33
94#define RESET_USB_OTG 34
95#define RESET_DDR 35
96#define RESET_AO_RESET 36
97#define RESET_BT656 37
98#define RESET_AHB_SRAM 38
99/* 39 */
100#define RESET_PARSER 40
101#define RESET_BLKMV 41
102#define RESET_ISA 42
103#define RESET_ETHERNET 43
104#define RESET_SD_EMMC_A 44
105#define RESET_SD_EMMC_B 45
106#define RESET_SD_EMMC_C 46
107#define RESET_ROM_BOOT 47
108#define RESET_SYS_CPU_0 48
109#define RESET_SYS_CPU_1 49
110#define RESET_SYS_CPU_2 50
111#define RESET_SYS_CPU_3 51
112#define RESET_SYS_CPU_CORE_0 52
113#define RESET_SYS_CPU_CORE_1 53
114#define RESET_SYS_CPU_CORE_2 54
115#define RESET_SYS_CPU_CORE_3 55
116#define RESET_SYS_PLL_DIV 56
117#define RESET_SYS_CPU_AXI 57
118#define RESET_SYS_CPU_L2 58
119#define RESET_SYS_CPU_P 59
120#define RESET_SYS_CPU_MBIST 60
121/* 61 */
122/* 62 */
123/* 63 */
124/* RESET2 */
125#define RESET_VD_RMEM 64
126#define RESET_AUDIN 65
127#define RESET_HDMI_TX 66
128/* 67 */
129/* 68 */
130/* 69 */
131#define RESET_GE2D 70
132#define RESET_PARSER_REG 71
133#define RESET_PARSER_FETCH 72
134#define RESET_PARSER_CTL 73
135#define RESET_PARSER_TOP 74
136/* 75 */
137/* 76 */
138#define RESET_AO_CPU_RESET 77
139#define RESET_MALI 78
140#define RESET_HDMI_SYSTEM_RESET 79
141/* 80-95 */
142/* RESET3 */
143#define RESET_RING_OSCILLATOR 96
144#define RESET_SYS_CPU 97
145#define RESET_EFUSE 98
146#define RESET_SYS_CPU_BVCI 99
147#define RESET_AIFIFO 100
148#define RESET_TVFE 101
149#define RESET_AHB_BRIDGE_CNTL 102
150/* 103 */
151#define RESET_AUDIO_DAC 104
152#define RESET_DEMUX_TOP 105
153#define RESET_DEMUX_DES 106
154#define RESET_DEMUX_S2P_0 107
155#define RESET_DEMUX_S2P_1 108
156#define RESET_DEMUX_RESET_0 109
157#define RESET_DEMUX_RESET_1 110
158#define RESET_DEMUX_RESET_2 111
159/* 112-127 */
160/* RESET4 */
161/* 128 */
162/* 129 */
163/* 130 */
164/* 131 */
165#define RESET_DVIN_RESET 132
166#define RESET_RDMA 133
167#define RESET_VENCI 134
168#define RESET_VENCP 135
169/* 136 */
170#define RESET_VDAC 137
171#define RESET_RTC 138
172/* 139 */
173#define RESET_VDI6 140
174#define RESET_VENCL 141
175#define RESET_I2C_MASTER_2 142
176#define RESET_I2C_MASTER_1 143
177/* 144-159 */
178/* RESET5 */
179/* 160-191 */
180/* RESET6 */
181#define RESET_PERIPHS_GENERAL 192
182#define RESET_PERIPHS_SPICC 193
183#define RESET_PERIPHS_SMART_CARD 194
184#define RESET_PERIPHS_SAR_ADC 195
185#define RESET_PERIPHS_I2C_MASTER_0 196
186#define RESET_SANA 197
187/* 198 */
188#define RESET_PERIPHS_STREAM_INTERFACE 199
189#define RESET_PERIPHS_SDIO 200
190#define RESET_PERIPHS_UART_0 201
191#define RESET_PERIPHS_UART_1_2 202
192#define RESET_PERIPHS_ASYNC_0 203
193#define RESET_PERIPHS_ASYNC_1 204
194#define RESET_PERIPHS_SPI_0 205
195#define RESET_PERIPHS_SDHC 206
196#define RESET_UART_SLIP 207
197/* 208-223 */
198/* RESET7 */
199#define RESET_USB_DDR_0 224
200#define RESET_USB_DDR_1 225
201#define RESET_USB_DDR_2 226
202#define RESET_USB_DDR_3 227
203/* 228 */
204#define RESET_DEVICE_MMC_ARB 229
205/* 230 */
206#define RESET_VID_LOCK 231
207#define RESET_A9_DMC_PIPEL 232
208/* 233-255 */
209
210#endif
diff --git a/include/dt-bindings/reset/amlogic,meson8b-reset.h b/include/dt-bindings/reset/amlogic,meson8b-reset.h
new file mode 100644
index 000000000000..614aff2c7aff
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson8b-reset.h
@@ -0,0 +1,175 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * BSD LICENSE
25 *
26 * Copyright (c) 2016 BayLibre, SAS.
27 * Author: Neil Armstrong <narmstrong@baylibre.com>
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
56#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
57
58/* RESET0 */
59#define RESET_HIU 0
60#define RESET_VLD 1
61#define RESET_IQIDCT 2
62#define RESET_MC 3
63/* 8 */
64#define RESET_VIU 5
65#define RESET_AIU 6
66#define RESET_MCPU 7
67#define RESET_CCPU 8
68#define RESET_PMUX 9
69#define RESET_VENC 10
70#define RESET_ASSIST 11
71#define RESET_AFIFO2 12
72#define RESET_MDEC 13
73#define RESET_VLD_PART 14
74#define RESET_VIFIFO 15
75/* 16-31 */
76/* RESET1 */
77/* 32 */
78#define RESET_DEMUX 33
79#define RESET_USB_OTG 34
80#define RESET_DDR 35
81#define RESET_VDAC_1 36
82#define RESET_BT656 37
83#define RESET_AHB_SRAM 38
84#define RESET_AHB_BRIDGE 39
85#define RESET_PARSER 40
86#define RESET_BLKMV 41
87#define RESET_ISA 42
88#define RESET_ETHERNET 43
89#define RESET_ABUF 44
90#define RESET_AHB_DATA 45
91#define RESET_AHB_CNTL 46
92#define RESET_ROM_BOOT 47
93/* 48-63 */
94/* RESET2 */
95#define RESET_VD_RMEM 64
96#define RESET_AUDIN 65
97#define RESET_DBLK 66
98#define RESET_PIC_DC 66
99#define RESET_PSC 66
100#define RESET_NAND 66
101#define RESET_GE2D 70
102#define RESET_PARSER_REG 71
103#define RESET_PARSER_FETCH 72
104#define RESET_PARSER_CTL 73
105#define RESET_PARSER_TOP 74
106#define RESET_HDMI_APB 75
107#define RESET_AUDIO_APB 76
108#define RESET_MEDIA_CPU 77
109#define RESET_MALI 78
110#define RESET_HDMI_SYSTEM_RESET 79
111/* 80-95 */
112/* RESET3 */
113#define RESET_RING_OSCILLATOR 96
114#define RESET_SYS_CPU_0 97
115#define RESET_EFUSE 98
116#define RESET_SYS_CPU_BVCI 99
117#define RESET_AIFIFO 100
118#define RESET_AUDIO_PLL_MODULATOR 101
119#define RESET_AHB_BRIDGE_CNTL 102
120#define RESET_SYS_CPU_1 103
121#define RESET_AUDIO_DAC 104
122#define RESET_DEMUX_TOP 105
123#define RESET_DEMUX_DES 106
124#define RESET_DEMUX_S2P_0 107
125#define RESET_DEMUX_S2P_1 108
126#define RESET_DEMUX_RESET_0 109
127#define RESET_DEMUX_RESET_1 110
128#define RESET_DEMUX_RESET_2 111
129/* 112-127 */
130/* RESET4 */
131#define RESET_PL310 128
132#define RESET_A5_APB 129
133#define RESET_A5_AXI 130
134#define RESET_A5 131
135#define RESET_DVIN 132
136#define RESET_RDMA 133
137#define RESET_VENCI 134
138#define RESET_VENCP 135
139#define RESET_VENCT 136
140#define RESET_VDAC_4 137
141#define RESET_RTC 138
142#define RESET_A5_DEBUG 139
143#define RESET_VDI6 140
144#define RESET_VENCL 141
145/* 142-159 */
146/* RESET5 */
147#define RESET_DDR_PLL 160
148#define RESET_MISC_PLL 161
149#define RESET_SYS_PLL 162
150#define RESET_HPLL_PLL 163
151#define RESET_AUDIO_PLL 164
152#define RESET_VID2_PLL 165
153/* 166-191 */
154/* RESET6 */
155#define RESET_PERIPHS_GENERAL 192
156#define RESET_PERIPHS_IR_REMOTE 193
157#define RESET_PERIPHS_SMART_CARD 194
158#define RESET_PERIPHS_SAR_ADC 195
159#define RESET_PERIPHS_I2C_MASTER_0 196
160#define RESET_PERIPHS_I2C_MASTER_1 197
161#define RESET_PERIPHS_I2C_SLAVE 198
162#define RESET_PERIPHS_STREAM_INTERFACE 199
163#define RESET_PERIPHS_SDIO 200
164#define RESET_PERIPHS_UART_0 201
165#define RESET_PERIPHS_UART_1 202
166#define RESET_PERIPHS_ASYNC_0 203
167#define RESET_PERIPHS_ASYNC_1 204
168#define RESET_PERIPHS_SPI_0 205
169#define RESET_PERIPHS_SPI_1 206
170#define RESET_PERIPHS_LED_PWM 207
171/* 208-223 */
172/* RESET7 */
173/* 224-255 */
174
175#endif
diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h
index ca08a7e5248e..322ec5335b65 100644
--- a/include/dt-bindings/reset/hisi,hi6220-resets.h
+++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
@@ -64,4 +64,12 @@
64#define PERIPH_RSDIST9_CARM_SOCDBG 0x507 64#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
65#define PERIPH_RSDIST9_CARM_ETM 0x508 65#define PERIPH_RSDIST9_CARM_ETM 0x508
66 66
67#define MEDIA_G3D 0
68#define MEDIA_CODEC_VPU 2
69#define MEDIA_CODEC_JPEG 3
70#define MEDIA_ISP 4
71#define MEDIA_ADE 5
72#define MEDIA_MMU 6
73#define MEDIA_XG2RAM1 7
74
67#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 75#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h
new file mode 100644
index 000000000000..884fd91df8e9
--- /dev/null
+++ b/include/dt-bindings/reset/ti-syscon.h
@@ -0,0 +1,38 @@
1/*
2 * TI Syscon Reset definitions
3 *
4 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
18#define __DT_BINDINGS_RESET_TI_SYSCON_H__
19
20/*
21 * The reset does not support the feature and corresponding
22 * values are not valid
23 */
24#define ASSERT_NONE (1 << 0)
25#define DEASSERT_NONE (1 << 1)
26#define STATUS_NONE (1 << 2)
27
28/* When set this function is activated by setting(vs clearing) this bit */
29#define ASSERT_SET (1 << 3)
30#define DEASSERT_SET (1 << 4)
31#define STATUS_SET (1 << 5)
32
33/* The following are the inverse of the above and are added for consistency */
34#define ASSERT_CLEAR (0 << 3)
35#define DEASSERT_CLEAR (0 << 4)
36#define STATUS_CLEAR (0 << 5)
37
38#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 17:34:46 -0400