diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-04-13 10:44:23 -0400 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-04-14 21:01:58 -0400 |
| commit | 839a04d847f5871516f500091519c52dc40fe01d (patch) | |
| tree | 51a8b76e3e69b128d3925528d4ae91a57c5d30be /include/dt-bindings/power | |
| parent | 353cf9961acf5e0db8a6cb6f24333ad76dacb8fc (diff) | |
soc: renesas: Add r8a7795 SYSC PM Domain Binding Definitions
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'include/dt-bindings/power')
| -rw-r--r-- | include/dt-bindings/power/r8a7795-sysc.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h new file mode 100644 index 000000000000..ee2e26ba605e --- /dev/null +++ b/include/dt-bindings/power/r8a7795-sysc.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2016 Glider bvba | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; version 2 of the License. | ||
| 7 | */ | ||
| 8 | #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ | ||
| 9 | #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ | ||
| 10 | |||
| 11 | /* | ||
| 12 | * These power domain indices match the numbers of the interrupt bits | ||
| 13 | * representing the power areas in the various Interrupt Registers | ||
| 14 | * (e.g. SYSCISR, Interrupt Status Register) | ||
| 15 | */ | ||
| 16 | |||
| 17 | #define R8A7795_PD_CA57_CPU0 0 | ||
| 18 | #define R8A7795_PD_CA57_CPU1 1 | ||
| 19 | #define R8A7795_PD_CA57_CPU2 2 | ||
| 20 | #define R8A7795_PD_CA57_CPU3 3 | ||
| 21 | #define R8A7795_PD_CA53_CPU0 5 | ||
| 22 | #define R8A7795_PD_CA53_CPU1 6 | ||
| 23 | #define R8A7795_PD_CA53_CPU2 7 | ||
| 24 | #define R8A7795_PD_CA53_CPU3 8 | ||
| 25 | #define R8A7795_PD_A3VP 9 | ||
| 26 | #define R8A7795_PD_CA57_SCU 12 | ||
| 27 | #define R8A7795_PD_CR7 13 | ||
| 28 | #define R8A7795_PD_A3VC 14 | ||
| 29 | #define R8A7795_PD_3DG_A 17 | ||
| 30 | #define R8A7795_PD_3DG_B 18 | ||
| 31 | #define R8A7795_PD_3DG_C 19 | ||
| 32 | #define R8A7795_PD_3DG_D 20 | ||
| 33 | #define R8A7795_PD_CA53_SCU 21 | ||
| 34 | #define R8A7795_PD_3DG_E 22 | ||
| 35 | #define R8A7795_PD_A3IR 24 | ||
| 36 | #define R8A7795_PD_A2VC0 25 | ||
| 37 | #define R8A7795_PD_A2VC1 26 | ||
| 38 | |||
| 39 | /* Always-on power area */ | ||
| 40 | #define R8A7795_PD_ALWAYS_ON 32 | ||
| 41 | |||
| 42 | #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ | ||
