diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-01-25 05:22:54 -0500 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-01-25 10:18:24 -0500 |
| commit | fa3bc04ef8ccccfe47db1f4030a7a43569956402 (patch) | |
| tree | 33a64f2a399111dc8beb56fab1d953125d50afd9 /drivers | |
| parent | f1d912996fc054f1d7059b23371cd623692724ce (diff) | |
soc/tegra: pmc: Explicitly initialize all fields
It's not strictly necessary to initialize the fields in struct
tegra_pmc_soc if they are 0/false. However, we already initialize them
explicitly even if unnecessary, so keep doing that for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/soc/tegra/pmc.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index da0b6680c772..dba89fc81a04 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c | |||
| @@ -2069,6 +2069,8 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { | |||
| 2069 | .cpu_powergates = NULL, | 2069 | .cpu_powergates = NULL, |
| 2070 | .has_tsense_reset = false, | 2070 | .has_tsense_reset = false, |
| 2071 | .has_gpu_clamps = false, | 2071 | .has_gpu_clamps = false, |
| 2072 | .needs_mbist_war = false, | ||
| 2073 | .has_impl_33v_pwr = false, | ||
| 2072 | .num_io_pads = 0, | 2074 | .num_io_pads = 0, |
| 2073 | .io_pads = NULL, | 2075 | .io_pads = NULL, |
| 2074 | .num_pin_descs = 0, | 2076 | .num_pin_descs = 0, |
| @@ -2113,6 +2115,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { | |||
| 2113 | .cpu_powergates = tegra30_cpu_powergates, | 2115 | .cpu_powergates = tegra30_cpu_powergates, |
| 2114 | .has_tsense_reset = true, | 2116 | .has_tsense_reset = true, |
| 2115 | .has_gpu_clamps = false, | 2117 | .has_gpu_clamps = false, |
| 2118 | .needs_mbist_war = false, | ||
| 2116 | .has_impl_33v_pwr = false, | 2119 | .has_impl_33v_pwr = false, |
| 2117 | .num_io_pads = 0, | 2120 | .num_io_pads = 0, |
| 2118 | .io_pads = NULL, | 2121 | .io_pads = NULL, |
| @@ -2162,6 +2165,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { | |||
| 2162 | .cpu_powergates = tegra114_cpu_powergates, | 2165 | .cpu_powergates = tegra114_cpu_powergates, |
| 2163 | .has_tsense_reset = true, | 2166 | .has_tsense_reset = true, |
| 2164 | .has_gpu_clamps = false, | 2167 | .has_gpu_clamps = false, |
| 2168 | .needs_mbist_war = false, | ||
| 2165 | .has_impl_33v_pwr = false, | 2169 | .has_impl_33v_pwr = false, |
| 2166 | .num_io_pads = 0, | 2170 | .num_io_pads = 0, |
| 2167 | .io_pads = NULL, | 2171 | .io_pads = NULL, |
| @@ -2271,6 +2275,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { | |||
| 2271 | .cpu_powergates = tegra124_cpu_powergates, | 2275 | .cpu_powergates = tegra124_cpu_powergates, |
| 2272 | .has_tsense_reset = true, | 2276 | .has_tsense_reset = true, |
| 2273 | .has_gpu_clamps = true, | 2277 | .has_gpu_clamps = true, |
| 2278 | .needs_mbist_war = false, | ||
| 2274 | .has_impl_33v_pwr = false, | 2279 | .has_impl_33v_pwr = false, |
| 2275 | .num_io_pads = ARRAY_SIZE(tegra124_io_pads), | 2280 | .num_io_pads = ARRAY_SIZE(tegra124_io_pads), |
| 2276 | .io_pads = tegra124_io_pads, | 2281 | .io_pads = tegra124_io_pads, |
| @@ -2375,8 +2380,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { | |||
| 2375 | .cpu_powergates = tegra210_cpu_powergates, | 2380 | .cpu_powergates = tegra210_cpu_powergates, |
| 2376 | .has_tsense_reset = true, | 2381 | .has_tsense_reset = true, |
| 2377 | .has_gpu_clamps = true, | 2382 | .has_gpu_clamps = true, |
| 2378 | .has_impl_33v_pwr = false, | ||
| 2379 | .needs_mbist_war = true, | 2383 | .needs_mbist_war = true, |
| 2384 | .has_impl_33v_pwr = false, | ||
| 2380 | .num_io_pads = ARRAY_SIZE(tegra210_io_pads), | 2385 | .num_io_pads = ARRAY_SIZE(tegra210_io_pads), |
| 2381 | .io_pads = tegra210_io_pads, | 2386 | .io_pads = tegra210_io_pads, |
| 2382 | .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), | 2387 | .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), |
| @@ -2499,6 +2504,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { | |||
| 2499 | .cpu_powergates = NULL, | 2504 | .cpu_powergates = NULL, |
| 2500 | .has_tsense_reset = false, | 2505 | .has_tsense_reset = false, |
| 2501 | .has_gpu_clamps = false, | 2506 | .has_gpu_clamps = false, |
| 2507 | .needs_mbist_war = false, | ||
| 2502 | .has_impl_33v_pwr = true, | 2508 | .has_impl_33v_pwr = true, |
| 2503 | .num_io_pads = ARRAY_SIZE(tegra186_io_pads), | 2509 | .num_io_pads = ARRAY_SIZE(tegra186_io_pads), |
| 2504 | .io_pads = tegra186_io_pads, | 2510 | .io_pads = tegra186_io_pads, |
| @@ -2577,6 +2583,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { | |||
| 2577 | .cpu_powergates = NULL, | 2583 | .cpu_powergates = NULL, |
| 2578 | .has_tsense_reset = false, | 2584 | .has_tsense_reset = false, |
| 2579 | .has_gpu_clamps = false, | 2585 | .has_gpu_clamps = false, |
| 2586 | .needs_mbist_war = false, | ||
| 2587 | .has_impl_33v_pwr = false, | ||
| 2580 | .num_io_pads = ARRAY_SIZE(tegra194_io_pads), | 2588 | .num_io_pads = ARRAY_SIZE(tegra194_io_pads), |
| 2581 | .io_pads = tegra194_io_pads, | 2589 | .io_pads = tegra194_io_pads, |
| 2582 | .regs = &tegra186_pmc_regs, | 2590 | .regs = &tegra186_pmc_regs, |
