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authorChristian König <christian.koenig@amd.com>2018-08-21 06:45:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 16:10:29 -0400
commitf5d850331ea9bdf18e68ae298cff35c7b7233993 (patch)
tree5bef3dd4a1605cbdecdd2870f1241ab23008fe78 /drivers
parentefb6706405963047fb312efbe1af2d7490b58261 (diff)
drm/amdgpu: implement soft_recovery for GFX8 v2
Try to kill waves on the SQ. v2: only for the GFX ring for now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 282dba6cce86..9de940a65c80 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6714,6 +6714,18 @@ static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6714 amdgpu_ring_write(ring, val); 6714 amdgpu_ring_write(ring, val);
6715} 6715}
6716 6716
6717static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6718{
6719 struct amdgpu_device *adev = ring->adev;
6720 uint32_t value = 0;
6721
6722 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6723 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6724 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6725 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6726 WREG32(mmSQ_CMD, value);
6727}
6728
6717static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6729static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6718 enum amdgpu_interrupt_state state) 6730 enum amdgpu_interrupt_state state)
6719{ 6731{
@@ -7171,6 +7183,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
7171 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec, 7183 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
7172 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec, 7184 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
7173 .emit_wreg = gfx_v8_0_ring_emit_wreg, 7185 .emit_wreg = gfx_v8_0_ring_emit_wreg,
7186 .soft_recovery = gfx_v8_0_ring_soft_recovery,
7174}; 7187};
7175 7188
7176static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { 7189static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {