drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1

Should be using PCIELaneLow for the low clock level.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index e5c27d12aa49..077b79938528 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3183,7 +3183,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
                         state_entry->ucPCIEGenLow);
         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
-                        state_entry->ucPCIELaneHigh);
+                        state_entry->ucPCIELaneLow);
 
         performance_level = &(smu7_power_state->performance_levels
                         [smu7_power_state->performance_level_count++]);