diff options
| author | Christoph Manszewski <c.manszewski@samsung.com> | 2018-11-28 10:32:11 -0500 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2018-12-05 03:34:50 -0500 |
| commit | e9e5ba93cb1f61c16298aade49ec2537d497f0d6 (patch) | |
| tree | eae727c99918047d3357c102b5d6fea15d2d70dc /drivers | |
| parent | af130280c613218a37675c6442650ca809f274c2 (diff) | |
drm/exynos: mixer: Fix color format setting
Fix color format decision based on height(pixels).
According to CEA-861-E:
"High Definition (HD) - A CE video format that, inclusively, has between
720 to 1080 active vertical lines (Vactive) lines per video frame."
Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20181128
using modetest.
Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_mixer.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 5a47af8e76c0..9cdae10fd36d 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c | |||
| @@ -384,14 +384,9 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) | |||
| 384 | { | 384 | { |
| 385 | u32 val; | 385 | u32 val; |
| 386 | 386 | ||
| 387 | switch (height) { | 387 | if (height < 720) { |
| 388 | case 480: | ||
| 389 | case 576: | ||
| 390 | val = MXR_CFG_RGB601_0_255; | 388 | val = MXR_CFG_RGB601_0_255; |
| 391 | break; | 389 | } else { |
| 392 | case 720: | ||
| 393 | case 1080: | ||
| 394 | default: | ||
| 395 | val = MXR_CFG_RGB709_16_235; | 390 | val = MXR_CFG_RGB709_16_235; |
| 396 | /* Configure the BT.709 CSC matrix for full range RGB. */ | 391 | /* Configure the BT.709 CSC matrix for full range RGB. */ |
| 397 | mixer_reg_write(ctx, MXR_CM_COEFF_Y, | 392 | mixer_reg_write(ctx, MXR_CM_COEFF_Y, |
| @@ -401,7 +396,6 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) | |||
| 401 | MXR_CSC_CT(-0.102, -0.338, 0.440)); | 396 | MXR_CSC_CT(-0.102, -0.338, 0.440)); |
| 402 | mixer_reg_write(ctx, MXR_CM_COEFF_CR, | 397 | mixer_reg_write(ctx, MXR_CM_COEFF_CR, |
| 403 | MXR_CSC_CT( 0.440, -0.399, -0.040)); | 398 | MXR_CSC_CT( 0.440, -0.399, -0.040)); |
| 404 | break; | ||
| 405 | } | 399 | } |
| 406 | 400 | ||
| 407 | mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); | 401 | mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); |
