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authorRodrigo Vivi <rodrigo.vivi@intel.com>2017-12-22 13:13:23 -0500
committerRodrigo Vivi <rodrigo.vivi@intel.com>2017-12-22 13:13:23 -0500
commite329ef67a7b06a3ab9b28fca4464760d4d7f8d47 (patch)
tree0dcecb61052376686f79828d0a316828fae693c9 /drivers
parent757fffcfdffb6c0dd46c1b264091c36b4e5a86ae (diff)
parent4fafba2d73fcaf1b433c26e753a98ad4b231754a (diff)
Merge tag 'gvt-next-2017-12-22' of https://github.com/intel/gvt-linux into drm-intel-next-queued
gvt-next-2017-12-22: - more mmio switch optimization (Weinan) - cleanup i915_reg_t vs. offset usage (Zhenyu) - move write protect handler out of mmio handler (Zhenyu) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171222085141.vgewlvvni37dljdt@zhen-hp.sh.intel.com
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/gvt/cmd_parser.c39
-rw-r--r--drivers/gpu/drm/i915/gvt/display.c81
-rw-r--r--drivers/gpu/drm/i915/gvt/edid.c22
-rw-r--r--drivers/gpu/drm/i915/gvt/fb_decoder.c30
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.c37
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.h3
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.c1
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.h33
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c750
-rw-r--r--drivers/gpu/drm/i915/gvt/kvmgt.c4
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio.c57
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio.h7
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio_context.c238
-rw-r--r--drivers/gpu/drm/i915/gvt/trace.h15
-rw-r--r--drivers/gpu/drm/i915/gvt/vgpu.c24
15 files changed, 675 insertions, 666 deletions
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 18c45734c7a2..edec15d19538 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s,
825 return 0; 825 return 0;
826} 826}
827 827
828static inline bool is_mocs_mmio(unsigned int offset)
829{
830 return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
831 ((offset >= 0xb020) && (offset <= 0xb0a0));
832}
833
834static int mocs_cmd_reg_handler(struct parser_exec_state *s,
835 unsigned int offset, unsigned int index)
836{
837 if (!is_mocs_mmio(offset))
838 return -EINVAL;
839 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
840 return 0;
841}
842
828static int cmd_reg_handler(struct parser_exec_state *s, 843static int cmd_reg_handler(struct parser_exec_state *s,
829 unsigned int offset, unsigned int index, char *cmd) 844 unsigned int offset, unsigned int index, char *cmd)
830{ 845{
@@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s,
848 return 0; 863 return 0;
849 } 864 }
850 865
866 if (is_mocs_mmio(offset) &&
867 mocs_cmd_reg_handler(s, offset, index))
868 return -EINVAL;
869
851 if (is_force_nonpriv_mmio(offset) && 870 if (is_force_nonpriv_mmio(offset) &&
852 force_nonpriv_reg_handler(s, offset, index)) 871 force_nonpriv_reg_handler(s, offset, index))
853 return -EPERM; 872 return -EPERM;
@@ -1220,13 +1239,13 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1220 return 0; 1239 return 0;
1221 1240
1222 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1241 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1223 stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0); 1242 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1224 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & 1243 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1225 GENMASK(12, 10)) >> 10; 1244 GENMASK(12, 10)) >> 10;
1226 } else { 1245 } else {
1227 stride = (vgpu_vreg(s->vgpu, info->stride_reg) & 1246 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1228 GENMASK(15, 6)) >> 6; 1247 GENMASK(15, 6)) >> 6;
1229 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; 1248 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1230 } 1249 }
1231 1250
1232 if (stride != info->stride_val) 1251 if (stride != info->stride_val)
@@ -1245,21 +1264,21 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
1245 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; 1264 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1246 struct intel_vgpu *vgpu = s->vgpu; 1265 struct intel_vgpu *vgpu = s->vgpu;
1247 1266
1248 set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12), 1267 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1249 info->surf_val << 12); 1268 info->surf_val << 12);
1250 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1269 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1251 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0), 1270 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1252 info->stride_val); 1271 info->stride_val);
1253 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10), 1272 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1254 info->tile_val << 10); 1273 info->tile_val << 10);
1255 } else { 1274 } else {
1256 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6), 1275 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1257 info->stride_val << 6); 1276 info->stride_val << 6);
1258 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10), 1277 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1259 info->tile_val << 10); 1278 info->tile_val << 10);
1260 } 1279 }
1261 1280
1262 vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++; 1281 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1263 intel_vgpu_trigger_virtual_event(vgpu, info->event); 1282 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1264 return 0; 1283 return 0;
1265} 1284}
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 09185036bac8..dd96ffc878ac 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -59,7 +59,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59{ 59{
60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
61 61
62 if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63 return 0; 63 return 0;
64 64
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
@@ -74,7 +74,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
75 return -EINVAL; 75 return -EINVAL;
76 76
77 if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 77 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
78 return 1; 78 return 1;
79 79
80 if (edp_pipe_is_enabled(vgpu) && 80 if (edp_pipe_is_enabled(vgpu) &&
@@ -169,103 +169,105 @@ static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
169static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 169static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
170{ 170{
171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172 vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 172 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
173 SDE_PORTC_HOTPLUG_CPT | 173 SDE_PORTC_HOTPLUG_CPT |
174 SDE_PORTD_HOTPLUG_CPT); 174 SDE_PORTD_HOTPLUG_CPT);
175 175
176 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 176 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
177 vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 177 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
178 SDE_PORTE_HOTPLUG_SPT); 178 SDE_PORTE_HOTPLUG_SPT);
179 vgpu_vreg(vgpu, SKL_FUSE_STATUS) |= 179 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
180 SKL_FUSE_DOWNLOAD_STATUS | 180 SKL_FUSE_DOWNLOAD_STATUS |
181 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 181 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
182 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 182 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
183 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 183 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
184 vgpu_vreg(vgpu, LCPLL1_CTL) |= 184 vgpu_vreg_t(vgpu, LCPLL1_CTL) |=
185 LCPLL_PLL_ENABLE | 185 LCPLL_PLL_ENABLE |
186 LCPLL_PLL_LOCK; 186 LCPLL_PLL_LOCK;
187 vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE; 187 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
188 188
189 } 189 }
190 190
191 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 191 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
192 vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 192 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
193 vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 193 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
194 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 194 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
195 TRANS_DDI_PORT_MASK); 195 TRANS_DDI_PORT_MASK);
196 vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 196 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
197 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 197 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
198 (PORT_B << TRANS_DDI_PORT_SHIFT) | 198 (PORT_B << TRANS_DDI_PORT_SHIFT) |
199 TRANS_DDI_FUNC_ENABLE); 199 TRANS_DDI_FUNC_ENABLE);
200 if (IS_BROADWELL(dev_priv)) { 200 if (IS_BROADWELL(dev_priv)) {
201 vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) &= 201 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
202 ~PORT_CLK_SEL_MASK; 202 ~PORT_CLK_SEL_MASK;
203 vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) |= 203 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
204 PORT_CLK_SEL_LCPLL_810; 204 PORT_CLK_SEL_LCPLL_810;
205 } 205 }
206 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 206 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
207 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 207 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
208 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 208 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
209 } 209 }
210 210
211 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 211 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
212 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 212 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
213 vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
214 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 214 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
215 TRANS_DDI_PORT_MASK); 215 TRANS_DDI_PORT_MASK);
216 vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 216 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
217 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 217 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
218 (PORT_C << TRANS_DDI_PORT_SHIFT) | 218 (PORT_C << TRANS_DDI_PORT_SHIFT) |
219 TRANS_DDI_FUNC_ENABLE); 219 TRANS_DDI_FUNC_ENABLE);
220 if (IS_BROADWELL(dev_priv)) { 220 if (IS_BROADWELL(dev_priv)) {
221 vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) &= 221 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
222 ~PORT_CLK_SEL_MASK; 222 ~PORT_CLK_SEL_MASK;
223 vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) |= 223 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
224 PORT_CLK_SEL_LCPLL_810; 224 PORT_CLK_SEL_LCPLL_810;
225 } 225 }
226 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 226 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
227 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 227 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
228 vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 228 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
229 } 229 }
230 230
231 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 231 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
232 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 232 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
233 vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 233 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
234 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 234 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
235 TRANS_DDI_PORT_MASK); 235 TRANS_DDI_PORT_MASK);
236 vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 236 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
237 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 237 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
238 (PORT_D << TRANS_DDI_PORT_SHIFT) | 238 (PORT_D << TRANS_DDI_PORT_SHIFT) |
239 TRANS_DDI_FUNC_ENABLE); 239 TRANS_DDI_FUNC_ENABLE);
240 if (IS_BROADWELL(dev_priv)) { 240 if (IS_BROADWELL(dev_priv)) {
241 vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) &= 241 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
242 ~PORT_CLK_SEL_MASK; 242 ~PORT_CLK_SEL_MASK;
243 vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) |= 243 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
244 PORT_CLK_SEL_LCPLL_810; 244 PORT_CLK_SEL_LCPLL_810;
245 } 245 }
246 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 246 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
247 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 247 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
248 vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 248 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
249 } 249 }
250 250
251 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 251 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
252 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 252 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
253 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 253 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
254 } 254 }
255 255
256 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 256 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
257 if (IS_BROADWELL(dev_priv)) 257 if (IS_BROADWELL(dev_priv))
258 vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |= 258 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
259 GEN8_PORT_DP_A_HOTPLUG; 259 GEN8_PORT_DP_A_HOTPLUG;
260 else 260 else
261 vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 261 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
262 262
263 vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 263 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
264 } 264 }
265 265
266 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 266 /* Clear host CRT status, so guest couldn't detect this host CRT. */
267 if (IS_BROADWELL(dev_priv)) 267 if (IS_BROADWELL(dev_priv))
268 vgpu_vreg(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 268 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
269
270 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
269} 271}
270 272
271static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 273static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
@@ -282,7 +284,6 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
282static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 284static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
283 int type, unsigned int resolution) 285 int type, unsigned int resolution)
284{ 286{
285 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
286 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 287 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
287 288
288 if (WARN_ON(resolution >= GVT_EDID_NUM)) 289 if (WARN_ON(resolution >= GVT_EDID_NUM))
@@ -308,7 +309,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
308 port->type = type; 309 port->type = type;
309 310
310 emulate_monitor_status_change(vgpu); 311 emulate_monitor_status_change(vgpu);
311 vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 312
312 return 0; 313 return 0;
313} 314}
314 315
@@ -368,12 +369,12 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
368 if (!pipe_is_enabled(vgpu, pipe)) 369 if (!pipe_is_enabled(vgpu, pipe))
369 continue; 370 continue;
370 371
371 vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 372 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
372 intel_vgpu_trigger_virtual_event(vgpu, event); 373 intel_vgpu_trigger_virtual_event(vgpu, event);
373 } 374 }
374 375
375 if (pipe_is_enabled(vgpu, pipe)) { 376 if (pipe_is_enabled(vgpu, pipe)) {
376 vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 377 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
377 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 378 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
378 } 379 }
379} 380}
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 42cd09ec63fa..f61337632969 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -95,9 +95,9 @@ static inline int get_port_from_gmbus0(u32 gmbus0)
95 95
96static void reset_gmbus_controller(struct intel_vgpu *vgpu) 96static void reset_gmbus_controller(struct intel_vgpu *vgpu)
97{ 97{
98 vgpu_vreg(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; 98 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
99 if (!vgpu->display.i2c_edid.edid_available) 99 if (!vgpu->display.i2c_edid.edid_available)
100 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; 100 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
101 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; 101 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
102} 102}
103 103
@@ -123,16 +123,16 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
123 vgpu->display.i2c_edid.state = I2C_GMBUS; 123 vgpu->display.i2c_edid.state = I2C_GMBUS;
124 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; 124 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
125 125
126 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; 126 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
127 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; 127 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
128 128
129 if (intel_vgpu_has_monitor_on_port(vgpu, port) && 129 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
130 !intel_vgpu_port_is_dp(vgpu, port)) { 130 !intel_vgpu_port_is_dp(vgpu, port)) {
131 vgpu->display.i2c_edid.port = port; 131 vgpu->display.i2c_edid.port = port;
132 vgpu->display.i2c_edid.edid_available = true; 132 vgpu->display.i2c_edid.edid_available = true;
133 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; 133 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
134 } else 134 } else
135 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; 135 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
136 return 0; 136 return 0;
137} 137}
138 138
@@ -159,8 +159,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
159 * 2) HW_RDY bit asserted 159 * 2) HW_RDY bit asserted
160 */ 160 */
161 if (wvalue & GMBUS_SW_CLR_INT) { 161 if (wvalue & GMBUS_SW_CLR_INT) {
162 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; 162 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
163 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; 163 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
164 } 164 }
165 165
166 /* For virtualization, we suppose that HW is always ready, 166 /* For virtualization, we suppose that HW is always ready,
@@ -208,7 +208,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
208 * visible in gmbus interface) 208 * visible in gmbus interface)
209 */ 209 */
210 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE; 210 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
211 vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; 211 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
212 } 212 }
213 break; 213 break;
214 case NIDX_NS_W: 214 case NIDX_NS_W:
@@ -220,7 +220,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
220 * START (-->INDEX) -->DATA 220 * START (-->INDEX) -->DATA
221 */ 221 */
222 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE; 222 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
223 vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; 223 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
224 break; 224 break;
225 default: 225 default:
226 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n"); 226 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
@@ -256,7 +256,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
256 u32 reg_data = 0; 256 u32 reg_data = 0;
257 257
258 /* Data can only be recevied if previous settings correct */ 258 /* Data can only be recevied if previous settings correct */
259 if (vgpu_vreg(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) { 259 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
260 if (byte_left <= 0) { 260 if (byte_left <= 0) {
261 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 261 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
262 return 0; 262 return 0;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 6cc99543693f..6b50fe78dc1b 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -147,7 +147,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
147{ 147{
148 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 148 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
149 149
150 u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask; 150 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
151 u32 stride = stride_reg; 151 u32 stride = stride_reg;
152 152
153 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 153 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -209,7 +209,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
209 if (pipe >= I915_MAX_PIPES) 209 if (pipe >= I915_MAX_PIPES)
210 return -ENODEV; 210 return -ENODEV;
211 211
212 val = vgpu_vreg(vgpu, DSPCNTR(pipe)); 212 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
213 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE); 213 plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
214 if (!plane->enabled) 214 if (!plane->enabled)
215 return -ENODEV; 215 return -ENODEV;
@@ -244,7 +244,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
244 244
245 plane->hw_format = fmt; 245 plane->hw_format = fmt;
246 246
247 plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; 247 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
248 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { 248 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {
249 gvt_vgpu_err("invalid gma address: %lx\n", 249 gvt_vgpu_err("invalid gma address: %lx\n",
250 (unsigned long)plane->base); 250 (unsigned long)plane->base);
@@ -263,14 +263,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
263 (_PRI_PLANE_STRIDE_MASK >> 6) : 263 (_PRI_PLANE_STRIDE_MASK >> 6) :
264 _PRI_PLANE_STRIDE_MASK, plane->bpp); 264 _PRI_PLANE_STRIDE_MASK, plane->bpp);
265 265
266 plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> 266 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
267 _PIPE_H_SRCSZ_SHIFT; 267 _PIPE_H_SRCSZ_SHIFT;
268 plane->width += 1; 268 plane->width += 1;
269 plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) & 269 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
270 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; 270 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
271 plane->height += 1; /* raw height is one minus the real value */ 271 plane->height += 1; /* raw height is one minus the real value */
272 272
273 val = vgpu_vreg(vgpu, DSPTILEOFF(pipe)); 273 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
274 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> 274 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
275 _PRI_PLANE_X_OFF_SHIFT; 275 _PRI_PLANE_X_OFF_SHIFT;
276 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> 276 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
@@ -344,7 +344,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
344 if (pipe >= I915_MAX_PIPES) 344 if (pipe >= I915_MAX_PIPES)
345 return -ENODEV; 345 return -ENODEV;
346 346
347 val = vgpu_vreg(vgpu, CURCNTR(pipe)); 347 val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
348 mode = val & CURSOR_MODE; 348 mode = val & CURSOR_MODE;
349 plane->enabled = (mode != CURSOR_MODE_DISABLE); 349 plane->enabled = (mode != CURSOR_MODE_DISABLE);
350 if (!plane->enabled) 350 if (!plane->enabled)
@@ -370,7 +370,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
370 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", 370 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
371 alpha_plane, alpha_force); 371 alpha_plane, alpha_force);
372 372
373 plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; 373 plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
374 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { 374 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {
375 gvt_vgpu_err("invalid gma address: %lx\n", 375 gvt_vgpu_err("invalid gma address: %lx\n",
376 (unsigned long)plane->base); 376 (unsigned long)plane->base);
@@ -384,7 +384,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
384 return -EINVAL; 384 return -EINVAL;
385 } 385 }
386 386
387 val = vgpu_vreg(vgpu, CURPOS(pipe)); 387 val = vgpu_vreg_t(vgpu, CURPOS(pipe));
388 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; 388 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
389 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; 389 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
390 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; 390 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
@@ -424,7 +424,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
424 if (pipe >= I915_MAX_PIPES) 424 if (pipe >= I915_MAX_PIPES)
425 return -ENODEV; 425 return -ENODEV;
426 426
427 val = vgpu_vreg(vgpu, SPRCTL(pipe)); 427 val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
428 plane->enabled = !!(val & SPRITE_ENABLE); 428 plane->enabled = !!(val & SPRITE_ENABLE);
429 if (!plane->enabled) 429 if (!plane->enabled)
430 return -ENODEV; 430 return -ENODEV;
@@ -475,7 +475,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
475 475
476 plane->drm_format = drm_format; 476 plane->drm_format = drm_format;
477 477
478 plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; 478 plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
479 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { 479 if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {
480 gvt_vgpu_err("invalid gma address: %lx\n", 480 gvt_vgpu_err("invalid gma address: %lx\n",
481 (unsigned long)plane->base); 481 (unsigned long)plane->base);
@@ -489,10 +489,10 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
489 return -EINVAL; 489 return -EINVAL;
490 } 490 }
491 491
492 plane->stride = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) & 492 plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
493 _SPRITE_STRIDE_MASK; 493 _SPRITE_STRIDE_MASK;
494 494
495 val = vgpu_vreg(vgpu, SPRSIZE(pipe)); 495 val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
496 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> 496 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
497 _SPRITE_SIZE_HEIGHT_SHIFT; 497 _SPRITE_SIZE_HEIGHT_SHIFT;
498 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> 498 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
@@ -500,11 +500,11 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
500 plane->height += 1; /* raw height is one minus the real value */ 500 plane->height += 1; /* raw height is one minus the real value */
501 plane->width += 1; /* raw width is one minus the real value */ 501 plane->width += 1; /* raw width is one minus the real value */
502 502
503 val = vgpu_vreg(vgpu, SPRPOS(pipe)); 503 val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
504 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; 504 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
505 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; 505 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
506 506
507 val = vgpu_vreg(vgpu, SPROFFSET(pipe)); 507 val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
508 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> 508 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
509 _SPRITE_OFFSET_START_X_SHIFT; 509 _SPRITE_OFFSET_START_X_SHIFT;
510 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> 510 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 71a0f2b87b3a..c4f752eeadcc 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1968,6 +1968,39 @@ int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
1968 return ret; 1968 return ret;
1969} 1969}
1970 1970
1971int intel_vgpu_write_protect_handler(struct intel_vgpu *vgpu, u64 pa,
1972 void *p_data, unsigned int bytes)
1973{
1974 struct intel_gvt *gvt = vgpu->gvt;
1975 int ret = 0;
1976
1977 if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) {
1978 struct intel_vgpu_page_track *t;
1979
1980 mutex_lock(&gvt->lock);
1981
1982 t = intel_vgpu_find_tracked_page(vgpu, pa >> PAGE_SHIFT);
1983 if (t) {
1984 if (unlikely(vgpu->failsafe)) {
1985 /* remove write protection to prevent furture traps */
1986 intel_vgpu_clean_page_track(vgpu, t);
1987 } else {
1988 ret = t->handler(t, pa, p_data, bytes);
1989 if (ret) {
1990 gvt_err("guest page write error %d, "
1991 "gfn 0x%lx, pa 0x%llx, "
1992 "var 0x%x, len %d\n",
1993 ret, t->gfn, pa,
1994 *(u32 *)p_data, bytes);
1995 }
1996 }
1997 }
1998 mutex_unlock(&gvt->lock);
1999 }
2000 return ret;
2001}
2002
2003
1971static int alloc_scratch_pages(struct intel_vgpu *vgpu, 2004static int alloc_scratch_pages(struct intel_vgpu *vgpu,
1972 intel_gvt_gtt_type_t type) 2005 intel_gvt_gtt_type_t type)
1973{ 2006{
@@ -2244,7 +2277,7 @@ struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
2244int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu, 2277int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu,
2245 int page_table_level) 2278 int page_table_level)
2246{ 2279{
2247 u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0])); 2280 u64 *pdp = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
2248 struct intel_vgpu_mm *mm; 2281 struct intel_vgpu_mm *mm;
2249 2282
2250 if (WARN_ON((page_table_level != 4) && (page_table_level != 3))) 2283 if (WARN_ON((page_table_level != 4) && (page_table_level != 3)))
@@ -2279,7 +2312,7 @@ int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu,
2279int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu, 2312int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu,
2280 int page_table_level) 2313 int page_table_level)
2281{ 2314{
2282 u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0])); 2315 u64 *pdp = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
2283 struct intel_vgpu_mm *mm; 2316 struct intel_vgpu_mm *mm;
2284 2317
2285 if (WARN_ON((page_table_level != 4) && (page_table_level != 3))) 2318 if (WARN_ON((page_table_level != 4) && (page_table_level != 3)))
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index f98c1c19b4cb..4cc13b5934f1 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -308,4 +308,7 @@ int intel_vgpu_emulate_gtt_mmio_read(struct intel_vgpu *vgpu,
308int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, 308int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu,
309 unsigned int off, void *p_data, unsigned int bytes); 309 unsigned int off, void *p_data, unsigned int bytes);
310 310
311int intel_vgpu_write_protect_handler(struct intel_vgpu *vgpu, u64 pa,
312 void *p_data, unsigned int bytes);
313
311#endif /* _GVT_GTT_H_ */ 314#endif /* _GVT_GTT_H_ */
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 643bb961d40d..fac54f32d33f 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -183,6 +183,7 @@ static const struct intel_gvt_ops intel_gvt_ops = {
183 .get_gvt_attrs = intel_get_gvt_attrs, 183 .get_gvt_attrs = intel_get_gvt_attrs,
184 .vgpu_query_plane = intel_vgpu_query_plane, 184 .vgpu_query_plane = intel_vgpu_query_plane,
185 .vgpu_get_dmabuf = intel_vgpu_get_dmabuf, 185 .vgpu_get_dmabuf = intel_vgpu_get_dmabuf,
186 .write_protect_handler = intel_vgpu_write_protect_handler,
186}; 187};
187 188
188/** 189/**
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 1e9f11c8b7bb..7dc7a80213a8 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -412,23 +412,20 @@ void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
412void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 412void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
413 u32 fence, u64 value); 413 u32 fence, u64 value);
414 414
415/* Macros for easily accessing vGPU virtual/shadow register */ 415/* Macros for easily accessing vGPU virtual/shadow register.
416#define vgpu_vreg(vgpu, reg) \ 416 Explicitly seperate use for typed MMIO reg or real offset.*/
417 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 417#define vgpu_vreg_t(vgpu, reg) \
418#define vgpu_vreg8(vgpu, reg) \ 418 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
419 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 419#define vgpu_vreg(vgpu, offset) \
420#define vgpu_vreg16(vgpu, reg) \ 420 (*(u32 *)(vgpu->mmio.vreg + (offset)))
421 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 421#define vgpu_vreg64_t(vgpu, reg) \
422#define vgpu_vreg64(vgpu, reg) \ 422 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
423 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 423#define vgpu_vreg64(vgpu, offset) \
424#define vgpu_sreg(vgpu, reg) \ 424 (*(u64 *)(vgpu->mmio.vreg + (offset)))
425 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 425#define vgpu_sreg_t(vgpu, reg) \
426#define vgpu_sreg8(vgpu, reg) \ 426 (*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg)))
427 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 427#define vgpu_sreg(vgpu, offset) \
428#define vgpu_sreg16(vgpu, reg) \ 428 (*(u32 *)(vgpu->mmio.sreg + (offset)))
429 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
430#define vgpu_sreg64(vgpu, reg) \
431 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
432 429
433#define for_each_active_vgpu(gvt, vgpu, id) \ 430#define for_each_active_vgpu(gvt, vgpu, id) \
434 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 431 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
@@ -549,6 +546,8 @@ struct intel_gvt_ops {
549 struct attribute_group ***intel_vgpu_type_groups); 546 struct attribute_group ***intel_vgpu_type_groups);
550 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); 547 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
551 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); 548 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
549 int (*write_protect_handler)(struct intel_vgpu *, u64, void *,
550 unsigned int);
552}; 551};
553 552
554 553
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index c982867e7c2b..92d6468daeee 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -343,13 +343,13 @@ static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
343 write_vreg(vgpu, offset, p_data, bytes); 343 write_vreg(vgpu, offset, p_data, bytes);
344 344
345 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 345 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
346 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 346 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
347 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 347 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
348 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 348 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
349 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 349 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
350 350
351 } else 351 } else
352 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 352 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
353 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 353 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
354 | PP_CYCLE_DELAY_ACTIVE); 354 | PP_CYCLE_DELAY_ACTIVE);
355 return 0; 355 return 0;
@@ -503,7 +503,7 @@ static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
503 } else { 503 } else {
504 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 504 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
505 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 505 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
506 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 506 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
507 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 507 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
508 } 508 }
509 return 0; 509 return 0;
@@ -521,9 +521,9 @@ static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
521 521
522static int fdi_auto_training_started(struct intel_vgpu *vgpu) 522static int fdi_auto_training_started(struct intel_vgpu *vgpu)
523{ 523{
524 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 524 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
525 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 525 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
526 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 526 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
527 527
528 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 528 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
529 (rx_ctl & FDI_RX_ENABLE) && 529 (rx_ctl & FDI_RX_ENABLE) &&
@@ -564,12 +564,12 @@ static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
564 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 564 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
565 565
566 /* If imr bit has been masked */ 566 /* If imr bit has been masked */
567 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 567 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
568 return 0; 568 return 0;
569 569
570 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 570 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
571 == fdi_tx_check_bits) 571 == fdi_tx_check_bits)
572 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 572 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
573 == fdi_rx_check_bits)) 573 == fdi_rx_check_bits))
574 return 1; 574 return 1;
575 else 575 else
@@ -626,17 +626,17 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
626 if (ret < 0) 626 if (ret < 0)
627 return ret; 627 return ret;
628 if (ret) 628 if (ret)
629 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 629 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
630 630
631 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 631 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
632 if (ret < 0) 632 if (ret < 0)
633 return ret; 633 return ret;
634 if (ret) 634 if (ret)
635 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 635 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
636 636
637 if (offset == _FDI_RXA_CTL) 637 if (offset == _FDI_RXA_CTL)
638 if (fdi_auto_training_started(vgpu)) 638 if (fdi_auto_training_started(vgpu))
639 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 639 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
640 DP_TP_STATUS_AUTOTRAIN_DONE; 640 DP_TP_STATUS_AUTOTRAIN_DONE;
641 return 0; 641 return 0;
642} 642}
@@ -657,7 +657,7 @@ static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
657 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 657 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
658 if (data == 0x2) { 658 if (data == 0x2) {
659 status_reg = DP_TP_STATUS(index); 659 status_reg = DP_TP_STATUS(index);
660 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 660 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
661 } 661 }
662 return 0; 662 return 0;
663} 663}
@@ -721,7 +721,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
721 }; 721 };
722 722
723 write_vreg(vgpu, offset, p_data, bytes); 723 write_vreg(vgpu, offset, p_data, bytes);
724 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 724 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
725 725
726 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 726 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
727 return 0; 727 return 0;
@@ -742,7 +742,7 @@ static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
742 }; 742 };
743 743
744 write_vreg(vgpu, offset, p_data, bytes); 744 write_vreg(vgpu, offset, p_data, bytes);
745 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 745 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
746 746
747 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 747 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
748 return 0; 748 return 0;
@@ -1064,9 +1064,9 @@ static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1064static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1064static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1065 void *p_data, unsigned int bytes) 1065 void *p_data, unsigned int bytes)
1066{ 1066{
1067 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1067 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1068 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1068 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1069 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1069 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1070 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1070 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1071 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1071 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1072 sbi_offset); 1072 sbi_offset);
@@ -1091,13 +1091,13 @@ static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1091 1091
1092 vgpu_vreg(vgpu, offset) = data; 1092 vgpu_vreg(vgpu, offset) = data;
1093 1093
1094 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1094 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1095 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1095 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1096 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1096 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1097 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1097 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1098 1098
1099 write_virtual_sbi_register(vgpu, sbi_offset, 1099 write_virtual_sbi_register(vgpu, sbi_offset,
1100 vgpu_vreg(vgpu, SBI_DATA)); 1100 vgpu_vreg_t(vgpu, SBI_DATA));
1101 } 1101 }
1102 return 0; 1102 return 0;
1103} 1103}
@@ -1343,7 +1343,7 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1343{ 1343{
1344 u32 value = *(u32 *)p_data; 1344 u32 value = *(u32 *)p_data;
1345 u32 cmd = value & 0xff; 1345 u32 cmd = value & 0xff;
1346 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1346 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1347 1347
1348 switch (cmd) { 1348 switch (cmd) {
1349 case GEN9_PCODE_READ_MEM_LATENCY: 1349 case GEN9_PCODE_READ_MEM_LATENCY:
@@ -1586,7 +1586,7 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1586} 1586}
1587 1587
1588#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1588#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1589 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1589 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1590 f, s, am, rm, d, r, w); \ 1590 f, s, am, rm, d, r, w); \
1591 if (ret) \ 1591 if (ret) \
1592 return ret; \ 1592 return ret; \
@@ -1654,22 +1654,22 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1654 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1654 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1655 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1655 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1656 1656
1657#define RING_REG(base) (base + 0x28) 1657#define RING_REG(base) _MMIO((base) + 0x28)
1658 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1658 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1659#undef RING_REG 1659#undef RING_REG
1660 1660
1661#define RING_REG(base) (base + 0x134) 1661#define RING_REG(base) _MMIO((base) + 0x134)
1662 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1662 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1663#undef RING_REG 1663#undef RING_REG
1664 1664
1665#define RING_REG(base) (base + 0x6c) 1665#define RING_REG(base) _MMIO((base) + 0x6c)
1666 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1666 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1667#undef RING_REG 1667#undef RING_REG
1668 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1668 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1669 1669
1670 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL); 1670 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1671 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1671 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1672 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL); 1672 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1673 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1673 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1674 1674
1675 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1675 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
@@ -1679,7 +1679,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1679 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1679 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1680 1680
1681 /* RING MODE */ 1681 /* RING MODE */
1682#define RING_REG(base) (base + 0x29c) 1682#define RING_REG(base) _MMIO((base) + 0x29c)
1683 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1683 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1684 ring_mode_mmio_write); 1684 ring_mode_mmio_write);
1685#undef RING_REG 1685#undef RING_REG
@@ -1698,37 +1698,37 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1698 NULL, NULL); 1698 NULL, NULL);
1699 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1699 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1700 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1700 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1701 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1701 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1702 1702
1703 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1703 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1704 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1704 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1705 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1705 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1706 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1706 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1707 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1707 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1708 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1708 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1709 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1709 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1710 NULL, NULL); 1710 NULL, NULL);
1711 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1711 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1712 NULL, NULL); 1712 NULL, NULL);
1713 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); 1713 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1714 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); 1714 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1715 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); 1715 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1716 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL); 1716 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1717 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL); 1717 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1718 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL); 1718 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1719 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL); 1719 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1720 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1720 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1721 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1721 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1722 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1722 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1723 1723
1724 /* display */ 1724 /* display */
1725 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1725 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1726 MMIO_D(0x602a0, D_ALL); 1726 MMIO_D(_MMIO(0x602a0), D_ALL);
1727 1727
1728 MMIO_D(0x65050, D_ALL); 1728 MMIO_D(_MMIO(0x65050), D_ALL);
1729 MMIO_D(0x650b4, D_ALL); 1729 MMIO_D(_MMIO(0x650b4), D_ALL);
1730 1730
1731 MMIO_D(0xc4040, D_ALL); 1731 MMIO_D(_MMIO(0xc4040), D_ALL);
1732 MMIO_D(DERRMR, D_ALL); 1732 MMIO_D(DERRMR, D_ALL);
1733 1733
1734 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1734 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
@@ -1768,14 +1768,14 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1768 MMIO_D(CURBASE(PIPE_B), D_ALL); 1768 MMIO_D(CURBASE(PIPE_B), D_ALL);
1769 MMIO_D(CURBASE(PIPE_C), D_ALL); 1769 MMIO_D(CURBASE(PIPE_C), D_ALL);
1770 1770
1771 MMIO_D(0x700ac, D_ALL); 1771 MMIO_D(_MMIO(0x700ac), D_ALL);
1772 MMIO_D(0x710ac, D_ALL); 1772 MMIO_D(_MMIO(0x710ac), D_ALL);
1773 MMIO_D(0x720ac, D_ALL); 1773 MMIO_D(_MMIO(0x720ac), D_ALL);
1774 1774
1775 MMIO_D(0x70090, D_ALL); 1775 MMIO_D(_MMIO(0x70090), D_ALL);
1776 MMIO_D(0x70094, D_ALL); 1776 MMIO_D(_MMIO(0x70094), D_ALL);
1777 MMIO_D(0x70098, D_ALL); 1777 MMIO_D(_MMIO(0x70098), D_ALL);
1778 MMIO_D(0x7009c, D_ALL); 1778 MMIO_D(_MMIO(0x7009c), D_ALL);
1779 1779
1780 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1780 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1781 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1781 MMIO_D(DSPADDR(PIPE_A), D_ALL);
@@ -1951,24 +1951,24 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1951 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1951 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1952 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1952 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1953 1953
1954 MMIO_D(0x48268, D_ALL); 1954 MMIO_D(_MMIO(0x48268), D_ALL);
1955 1955
1956 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1956 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1957 gmbus_mmio_write); 1957 gmbus_mmio_write);
1958 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1958 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
1959 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1959 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1960 1960
1961 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1961 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1962 dp_aux_ch_ctl_mmio_write); 1962 dp_aux_ch_ctl_mmio_write);
1963 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1963 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1964 dp_aux_ch_ctl_mmio_write); 1964 dp_aux_ch_ctl_mmio_write);
1965 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1965 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1966 dp_aux_ch_ctl_mmio_write); 1966 dp_aux_ch_ctl_mmio_write);
1967 1967
1968 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 1968 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
1969 1969
1970 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1970 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
1971 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1971 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
1972 1972
1973 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1973 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1974 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1974 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
@@ -1980,30 +1980,30 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1980 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1980 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1981 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1981 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1982 1982
1983 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1983 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
1984 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1984 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
1985 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1985 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
1986 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1986 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
1987 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1987 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
1988 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1988 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
1989 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1989 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
1990 1990
1991 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1991 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
1992 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1992 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
1993 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1993 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
1994 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1994 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
1995 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1995 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
1996 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1996 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
1997 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1997 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
1998 1998
1999 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1999 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2000 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 2000 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2001 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 2001 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2002 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 2002 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2003 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 2003 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2004 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 2004 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2005 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 2005 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2006 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 2006 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2007 2007
2008 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2008 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2009 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2009 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
@@ -2021,38 +2021,38 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2021 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2021 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2022 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2022 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2023 2023
2024 MMIO_D(_FDI_RXA_MISC, D_ALL); 2024 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2025 MMIO_D(_FDI_RXB_MISC, D_ALL); 2025 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2026 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 2026 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2027 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 2027 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2028 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 2028 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2029 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 2029 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2030 2030
2031 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2031 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2032 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2032 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2033 MMIO_D(PCH_PP_STATUS, D_ALL); 2033 MMIO_D(PCH_PP_STATUS, D_ALL);
2034 MMIO_D(PCH_LVDS, D_ALL); 2034 MMIO_D(PCH_LVDS, D_ALL);
2035 MMIO_D(_PCH_DPLL_A, D_ALL); 2035 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2036 MMIO_D(_PCH_DPLL_B, D_ALL); 2036 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2037 MMIO_D(_PCH_FPA0, D_ALL); 2037 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2038 MMIO_D(_PCH_FPA1, D_ALL); 2038 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2039 MMIO_D(_PCH_FPB0, D_ALL); 2039 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2040 MMIO_D(_PCH_FPB1, D_ALL); 2040 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2041 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2041 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2042 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2042 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2043 MMIO_D(PCH_DPLL_SEL, D_ALL); 2043 MMIO_D(PCH_DPLL_SEL, D_ALL);
2044 2044
2045 MMIO_D(0x61208, D_ALL); 2045 MMIO_D(_MMIO(0x61208), D_ALL);
2046 MMIO_D(0x6120c, D_ALL); 2046 MMIO_D(_MMIO(0x6120c), D_ALL);
2047 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2047 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2048 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2048 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2049 2049
2050 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 2050 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2051 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 2051 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2052 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 2052 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2053 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 2053 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2054 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL); 2054 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2055 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL); 2055 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2056 2056
2057 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2057 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2058 PORTA_HOTPLUG_STATUS_MASK 2058 PORTA_HOTPLUG_STATUS_MASK
@@ -2074,11 +2074,11 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2074 2074
2075 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2075 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2076 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2076 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2077 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 2077 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2078 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 2078 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2079 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2079 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2080 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 2080 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2081 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 2081 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2082 2082
2083 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2083 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2084 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2084 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
@@ -2144,24 +2144,24 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2144 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2144 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2145 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2145 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2146 2146
2147 MMIO_D(0x60110, D_ALL); 2147 MMIO_D(_MMIO(0x60110), D_ALL);
2148 MMIO_D(0x61110, D_ALL); 2148 MMIO_D(_MMIO(0x61110), D_ALL);
2149 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2149 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2150 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2150 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2151 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2151 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2152 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2152 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2153 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2153 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2154 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2154 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2155 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2155 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2156 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2156 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2157 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2157 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2158 2158
2159 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2159 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2160 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2160 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2161 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2161 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2162 MMIO_D(SPLL_CTL, D_ALL); 2162 MMIO_D(SPLL_CTL, D_ALL);
2163 MMIO_D(_WRPLL_CTL1, D_ALL); 2163 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2164 MMIO_D(_WRPLL_CTL2, D_ALL); 2164 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2165 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2165 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2166 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2166 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2167 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2167 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
@@ -2172,15 +2172,15 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2172 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2172 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2173 2173
2174 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2174 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2175 MMIO_D(0x46508, D_ALL); 2175 MMIO_D(_MMIO(0x46508), D_ALL);
2176 2176
2177 MMIO_D(0x49080, D_ALL); 2177 MMIO_D(_MMIO(0x49080), D_ALL);
2178 MMIO_D(0x49180, D_ALL); 2178 MMIO_D(_MMIO(0x49180), D_ALL);
2179 MMIO_D(0x49280, D_ALL); 2179 MMIO_D(_MMIO(0x49280), D_ALL);
2180 2180
2181 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2181 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2182 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2182 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2183 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2183 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2184 2184
2185 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2185 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2186 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2186 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
@@ -2200,7 +2200,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2200 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2200 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2201 MMIO_D(PIXCLK_GATE, D_ALL); 2201 MMIO_D(PIXCLK_GATE, D_ALL);
2202 2202
2203 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 2203 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2204 dp_aux_ch_ctl_mmio_write); 2204 dp_aux_ch_ctl_mmio_write);
2205 2205
2206 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2206 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
@@ -2221,24 +2221,24 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2221 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2221 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2222 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2222 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2223 2223
2224 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2224 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2225 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2225 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2226 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2226 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2227 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2227 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2228 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2228 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2229 2229
2230 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2230 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2231 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2231 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2232 2232
2233 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2233 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2234 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2234 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2235 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2235 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2236 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2236 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2237 2237
2238 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2238 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2239 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2239 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2240 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2240 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2241 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2241 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2242 2242
2243 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2243 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2244 MMIO_D(FORCEWAKE_ACK, D_ALL); 2244 MMIO_D(FORCEWAKE_ACK, D_ALL);
@@ -2304,101 +2304,101 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2304 MMIO_D(GEN6_UCGCTL1, D_ALL); 2304 MMIO_D(GEN6_UCGCTL1, D_ALL);
2305 MMIO_D(GEN6_UCGCTL2, D_ALL); 2305 MMIO_D(GEN6_UCGCTL2, D_ALL);
2306 2306
2307 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2307 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2308 2308
2309 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2309 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2310 MMIO_D(0x13812c, D_ALL); 2310 MMIO_D(_MMIO(0x13812c), D_ALL);
2311 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2311 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2312 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2312 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2313 MMIO_D(HSW_IDICR, D_ALL); 2313 MMIO_D(HSW_IDICR, D_ALL);
2314 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2314 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2315 2315
2316 MMIO_D(0x3c, D_ALL); 2316 MMIO_D(_MMIO(0x3c), D_ALL);
2317 MMIO_D(0x860, D_ALL); 2317 MMIO_D(_MMIO(0x860), D_ALL);
2318 MMIO_D(ECOSKPD, D_ALL); 2318 MMIO_D(ECOSKPD, D_ALL);
2319 MMIO_D(0x121d0, D_ALL); 2319 MMIO_D(_MMIO(0x121d0), D_ALL);
2320 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2320 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2321 MMIO_D(0x41d0, D_ALL); 2321 MMIO_D(_MMIO(0x41d0), D_ALL);
2322 MMIO_D(GAC_ECO_BITS, D_ALL); 2322 MMIO_D(GAC_ECO_BITS, D_ALL);
2323 MMIO_D(0x6200, D_ALL); 2323 MMIO_D(_MMIO(0x6200), D_ALL);
2324 MMIO_D(0x6204, D_ALL); 2324 MMIO_D(_MMIO(0x6204), D_ALL);
2325 MMIO_D(0x6208, D_ALL); 2325 MMIO_D(_MMIO(0x6208), D_ALL);
2326 MMIO_D(0x7118, D_ALL); 2326 MMIO_D(_MMIO(0x7118), D_ALL);
2327 MMIO_D(0x7180, D_ALL); 2327 MMIO_D(_MMIO(0x7180), D_ALL);
2328 MMIO_D(0x7408, D_ALL); 2328 MMIO_D(_MMIO(0x7408), D_ALL);
2329 MMIO_D(0x7c00, D_ALL); 2329 MMIO_D(_MMIO(0x7c00), D_ALL);
2330 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2330 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2331 MMIO_D(0x911c, D_ALL); 2331 MMIO_D(_MMIO(0x911c), D_ALL);
2332 MMIO_D(0x9120, D_ALL); 2332 MMIO_D(_MMIO(0x9120), D_ALL);
2333 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2333 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2334 2334
2335 MMIO_D(GAB_CTL, D_ALL); 2335 MMIO_D(GAB_CTL, D_ALL);
2336 MMIO_D(0x48800, D_ALL); 2336 MMIO_D(_MMIO(0x48800), D_ALL);
2337 MMIO_D(0xce044, D_ALL); 2337 MMIO_D(_MMIO(0xce044), D_ALL);
2338 MMIO_D(0xe6500, D_ALL); 2338 MMIO_D(_MMIO(0xe6500), D_ALL);
2339 MMIO_D(0xe6504, D_ALL); 2339 MMIO_D(_MMIO(0xe6504), D_ALL);
2340 MMIO_D(0xe6600, D_ALL); 2340 MMIO_D(_MMIO(0xe6600), D_ALL);
2341 MMIO_D(0xe6604, D_ALL); 2341 MMIO_D(_MMIO(0xe6604), D_ALL);
2342 MMIO_D(0xe6700, D_ALL); 2342 MMIO_D(_MMIO(0xe6700), D_ALL);
2343 MMIO_D(0xe6704, D_ALL); 2343 MMIO_D(_MMIO(0xe6704), D_ALL);
2344 MMIO_D(0xe6800, D_ALL); 2344 MMIO_D(_MMIO(0xe6800), D_ALL);
2345 MMIO_D(0xe6804, D_ALL); 2345 MMIO_D(_MMIO(0xe6804), D_ALL);
2346 MMIO_D(PCH_GMBUS4, D_ALL); 2346 MMIO_D(PCH_GMBUS4, D_ALL);
2347 MMIO_D(PCH_GMBUS5, D_ALL); 2347 MMIO_D(PCH_GMBUS5, D_ALL);
2348 2348
2349 MMIO_D(0x902c, D_ALL); 2349 MMIO_D(_MMIO(0x902c), D_ALL);
2350 MMIO_D(0xec008, D_ALL); 2350 MMIO_D(_MMIO(0xec008), D_ALL);
2351 MMIO_D(0xec00c, D_ALL); 2351 MMIO_D(_MMIO(0xec00c), D_ALL);
2352 MMIO_D(0xec008 + 0x18, D_ALL); 2352 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2353 MMIO_D(0xec00c + 0x18, D_ALL); 2353 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2354 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2354 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2355 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2355 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2356 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2356 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2357 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2357 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2358 MMIO_D(0xec408, D_ALL); 2358 MMIO_D(_MMIO(0xec408), D_ALL);
2359 MMIO_D(0xec40c, D_ALL); 2359 MMIO_D(_MMIO(0xec40c), D_ALL);
2360 MMIO_D(0xec408 + 0x18, D_ALL); 2360 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2361 MMIO_D(0xec40c + 0x18, D_ALL); 2361 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2362 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2362 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2363 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2363 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2364 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2364 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2365 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2365 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2366 MMIO_D(0xfc810, D_ALL); 2366 MMIO_D(_MMIO(0xfc810), D_ALL);
2367 MMIO_D(0xfc81c, D_ALL); 2367 MMIO_D(_MMIO(0xfc81c), D_ALL);
2368 MMIO_D(0xfc828, D_ALL); 2368 MMIO_D(_MMIO(0xfc828), D_ALL);
2369 MMIO_D(0xfc834, D_ALL); 2369 MMIO_D(_MMIO(0xfc834), D_ALL);
2370 MMIO_D(0xfcc00, D_ALL); 2370 MMIO_D(_MMIO(0xfcc00), D_ALL);
2371 MMIO_D(0xfcc0c, D_ALL); 2371 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2372 MMIO_D(0xfcc18, D_ALL); 2372 MMIO_D(_MMIO(0xfcc18), D_ALL);
2373 MMIO_D(0xfcc24, D_ALL); 2373 MMIO_D(_MMIO(0xfcc24), D_ALL);
2374 MMIO_D(0xfd000, D_ALL); 2374 MMIO_D(_MMIO(0xfd000), D_ALL);
2375 MMIO_D(0xfd00c, D_ALL); 2375 MMIO_D(_MMIO(0xfd00c), D_ALL);
2376 MMIO_D(0xfd018, D_ALL); 2376 MMIO_D(_MMIO(0xfd018), D_ALL);
2377 MMIO_D(0xfd024, D_ALL); 2377 MMIO_D(_MMIO(0xfd024), D_ALL);
2378 MMIO_D(0xfd034, D_ALL); 2378 MMIO_D(_MMIO(0xfd034), D_ALL);
2379 2379
2380 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2380 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2381 MMIO_D(0x2054, D_ALL); 2381 MMIO_D(_MMIO(0x2054), D_ALL);
2382 MMIO_D(0x12054, D_ALL); 2382 MMIO_D(_MMIO(0x12054), D_ALL);
2383 MMIO_D(0x22054, D_ALL); 2383 MMIO_D(_MMIO(0x22054), D_ALL);
2384 MMIO_D(0x1a054, D_ALL); 2384 MMIO_D(_MMIO(0x1a054), D_ALL);
2385 2385
2386 MMIO_D(0x44070, D_ALL); 2386 MMIO_D(_MMIO(0x44070), D_ALL);
2387 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2387 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2388 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2388 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2389 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2389 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2390 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2390 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2391 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2391 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2392 2392
2393 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2393 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2394 MMIO_D(0x2b00, D_BDW_PLUS); 2394 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2395 MMIO_D(0x2360, D_BDW_PLUS); 2395 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2396 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2396 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2397 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2397 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2398 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2398 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2399 2399
2400 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2400 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2401 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2401 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2402 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2402 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2403 2403
2404 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2404 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
@@ -2412,24 +2412,24 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2412 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2412 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2413 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2414 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2414 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2415 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2415 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2416 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2416 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2417 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2417 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2418 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2418 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2419 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2419 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2420 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2420 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2421 2421
2422 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2422 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2423 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2423 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2424 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2424 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2425 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2425 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2426 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2426 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2427 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2427 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2428 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2429 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2429 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2430 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2430 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2431 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2431 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2432 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2432 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2433 return 0; 2433 return 0;
2434} 2434}
2435 2435
@@ -2503,40 +2503,40 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2503 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2503 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2504 mmio_read_from_hw, NULL); 2504 mmio_read_from_hw, NULL);
2505 2505
2506#define RING_REG(base) (base + 0xd0) 2506#define RING_REG(base) _MMIO((base) + 0xd0)
2507 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2507 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2508 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2508 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2509 ring_reset_ctl_write); 2509 ring_reset_ctl_write);
2510#undef RING_REG 2510#undef RING_REG
2511 2511
2512#define RING_REG(base) (base + 0x230) 2512#define RING_REG(base) _MMIO((base) + 0x230)
2513 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2513 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2514#undef RING_REG 2514#undef RING_REG
2515 2515
2516#define RING_REG(base) (base + 0x234) 2516#define RING_REG(base) _MMIO((base) + 0x234)
2517 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2517 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2518 NULL, NULL); 2518 NULL, NULL);
2519#undef RING_REG 2519#undef RING_REG
2520 2520
2521#define RING_REG(base) (base + 0x244) 2521#define RING_REG(base) _MMIO((base) + 0x244)
2522 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2522 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2523#undef RING_REG 2523#undef RING_REG
2524 2524
2525#define RING_REG(base) (base + 0x370) 2525#define RING_REG(base) _MMIO((base) + 0x370)
2526 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2526 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2527#undef RING_REG 2527#undef RING_REG
2528 2528
2529#define RING_REG(base) (base + 0x3a0) 2529#define RING_REG(base) _MMIO((base) + 0x3a0)
2530 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2530 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2531#undef RING_REG 2531#undef RING_REG
2532 2532
2533 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2533 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2534 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2534 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2535 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2535 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2536 MMIO_D(0x1c1d0, D_BDW_PLUS); 2536 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2537 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2537 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2538 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2538 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2539 MMIO_D(0x1c054, D_BDW_PLUS); 2539 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2540 2540
2541 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2541 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2542 2542
@@ -2545,7 +2545,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2545 2545
2546 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2546 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2547 2547
2548#define RING_REG(base) (base + 0x270) 2548#define RING_REG(base) _MMIO((base) + 0x270)
2549 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2549 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2550#undef RING_REG 2550#undef RING_REG
2551 2551
@@ -2558,10 +2558,10 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2558 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2558 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2559 2559
2560 MMIO_D(WM_MISC, D_BDW); 2560 MMIO_D(WM_MISC, D_BDW);
2561 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2561 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
2562 2562
2563 MMIO_D(0x66c00, D_BDW_PLUS); 2563 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2564 MMIO_D(0x66c04, D_BDW_PLUS); 2564 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2565 2565
2566 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2566 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2567 2567
@@ -2569,54 +2569,54 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2569 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2569 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2570 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2570 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2571 2571
2572 MMIO_D(0xfdc, D_BDW_PLUS); 2572 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2573 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2573 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2574 NULL, NULL); 2574 NULL, NULL);
2575 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2575 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2576 NULL, NULL); 2576 NULL, NULL);
2577 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2577 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2578 2578
2579 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2579 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2580 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2580 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2581 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2581 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2582 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL); 2582 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2583 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL); 2583 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2584 MMIO_D(0xb110, D_BDW); 2584 MMIO_D(_MMIO(0xb110), D_BDW);
2585 2585
2586 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2586 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2587 NULL, force_nonpriv_write); 2587 NULL, force_nonpriv_write);
2588 2588
2589 MMIO_D(0x44484, D_BDW_PLUS); 2589 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2590 MMIO_D(0x4448c, D_BDW_PLUS); 2590 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2591 2591
2592 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL); 2592 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2593 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2593 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2594 2594
2595 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL); 2595 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2596 2596
2597 MMIO_D(0x110000, D_BDW_PLUS); 2597 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2598 2598
2599 MMIO_D(0x48400, D_BDW_PLUS); 2599 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2600 2600
2601 MMIO_D(0x6e570, D_BDW_PLUS); 2601 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2602 MMIO_D(0x65f10, D_BDW_PLUS); 2602 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2603 2603
2604 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2604 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2605 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2605 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2606 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2606 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2607 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2607 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2608 2608
2609 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL); 2609 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2610 2610
2611 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2611 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2612 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2612 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2613 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2613 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2614 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2614 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2615 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2615 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2616 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2616 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2617 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2617 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2618 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2618 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2619 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2619 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2620 return 0; 2620 return 0;
2621} 2621}
2622 2622
@@ -2632,11 +2632,11 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2632 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2632 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2633 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2633 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2634 2634
2635 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2635 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2636 dp_aux_ch_ctl_mmio_write); 2636 dp_aux_ch_ctl_mmio_write);
2637 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2637 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2638 dp_aux_ch_ctl_mmio_write); 2638 dp_aux_ch_ctl_mmio_write);
2639 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2639 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2640 dp_aux_ch_ctl_mmio_write); 2640 dp_aux_ch_ctl_mmio_write);
2641 2641
2642 /* 2642 /*
@@ -2647,26 +2647,26 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2647 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2647 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2648 skl_power_well_ctl_write); 2648 skl_power_well_ctl_write);
2649 2649
2650 MMIO_D(0xa210, D_SKL_PLUS); 2650 MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
2651 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2651 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2652 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2652 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2653 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2653 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2654 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL); 2654 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL);
2655 MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL); 2655 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL);
2656 MMIO_D(0x45504, D_SKL_PLUS); 2656 MMIO_D(_MMIO(0x45504), D_SKL_PLUS);
2657 MMIO_D(0x45520, D_SKL_PLUS); 2657 MMIO_D(_MMIO(0x45520), D_SKL_PLUS);
2658 MMIO_D(0x46000, D_SKL_PLUS); 2658 MMIO_D(_MMIO(0x46000), D_SKL_PLUS);
2659 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write); 2659 MMIO_DH(_MMIO(0x46010), D_SKL | D_KBL, NULL, skl_lcpll_write);
2660 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write); 2660 MMIO_DH(_MMIO(0x46014), D_SKL | D_KBL, NULL, skl_lcpll_write);
2661 MMIO_D(0x6C040, D_SKL | D_KBL); 2661 MMIO_D(_MMIO(0x6C040), D_SKL | D_KBL);
2662 MMIO_D(0x6C048, D_SKL | D_KBL); 2662 MMIO_D(_MMIO(0x6C048), D_SKL | D_KBL);
2663 MMIO_D(0x6C050, D_SKL | D_KBL); 2663 MMIO_D(_MMIO(0x6C050), D_SKL | D_KBL);
2664 MMIO_D(0x6C044, D_SKL | D_KBL); 2664 MMIO_D(_MMIO(0x6C044), D_SKL | D_KBL);
2665 MMIO_D(0x6C04C, D_SKL | D_KBL); 2665 MMIO_D(_MMIO(0x6C04C), D_SKL | D_KBL);
2666 MMIO_D(0x6C054, D_SKL | D_KBL); 2666 MMIO_D(_MMIO(0x6C054), D_SKL | D_KBL);
2667 MMIO_D(0x6c058, D_SKL | D_KBL); 2667 MMIO_D(_MMIO(0x6c058), D_SKL | D_KBL);
2668 MMIO_D(0x6c05c, D_SKL | D_KBL); 2668 MMIO_D(_MMIO(0x6c05c), D_SKL | D_KBL);
2669 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL); 2669 MMIO_DH(_MMIO(0x6c060), D_SKL | D_KBL, dpll_status_read, NULL);
2670 2670
2671 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2671 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2672 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2672 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
@@ -2755,105 +2755,105 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2755 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2755 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2756 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2756 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2757 2757
2758 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2758 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2759 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2759 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2760 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2760 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2761 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); 2761 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2762 2762
2763 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2763 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2764 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2764 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2765 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2765 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2766 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); 2766 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2767 2767
2768 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2768 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2769 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2769 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2770 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2770 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2771 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); 2771 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2772 2772
2773 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2773 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2774 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2774 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2775 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2775 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2776 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); 2776 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2777 2777
2778 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2778 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2779 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2779 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2780 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2780 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2781 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); 2781 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2782 2782
2783 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2783 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2784 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2784 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2785 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2785 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2786 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); 2786 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2787 2787
2788 MMIO_D(0x70380, D_SKL_PLUS); 2788 MMIO_D(_MMIO(0x70380), D_SKL_PLUS);
2789 MMIO_D(0x71380, D_SKL_PLUS); 2789 MMIO_D(_MMIO(0x71380), D_SKL_PLUS);
2790 MMIO_D(0x72380, D_SKL_PLUS); 2790 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
2791 MMIO_D(0x7039c, D_SKL_PLUS); 2791 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS);
2792 2792
2793 MMIO_D(0x8f074, D_SKL | D_KBL); 2793 MMIO_D(_MMIO(0x8f074), D_SKL | D_KBL);
2794 MMIO_D(0x8f004, D_SKL | D_KBL); 2794 MMIO_D(_MMIO(0x8f004), D_SKL | D_KBL);
2795 MMIO_D(0x8f034, D_SKL | D_KBL); 2795 MMIO_D(_MMIO(0x8f034), D_SKL | D_KBL);
2796 2796
2797 MMIO_D(0xb11c, D_SKL | D_KBL); 2797 MMIO_D(_MMIO(0xb11c), D_SKL | D_KBL);
2798 2798
2799 MMIO_D(0x51000, D_SKL | D_KBL); 2799 MMIO_D(_MMIO(0x51000), D_SKL | D_KBL);
2800 MMIO_D(0x6c00c, D_SKL_PLUS); 2800 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS);
2801 2801
2802 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2802 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2803 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2803 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2804 2804
2805 MMIO_D(0xd08, D_SKL_PLUS); 2805 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
2806 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2806 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2807 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2807 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2808 2808
2809 /* TRTT */ 2809 /* TRTT */
2810 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2810 MMIO_DFH(_MMIO(0x4de0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2811 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2811 MMIO_DFH(_MMIO(0x4de4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2812 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2812 MMIO_DFH(_MMIO(0x4de8), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2813 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2813 MMIO_DFH(_MMIO(0x4dec), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2814 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2814 MMIO_DFH(_MMIO(0x4df0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2815 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write); 2815 MMIO_DFH(_MMIO(0x4df4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
2816 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write); 2816 MMIO_DH(_MMIO(0x4dfc), D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
2817 2817
2818 MMIO_D(0x45008, D_SKL | D_KBL); 2818 MMIO_D(_MMIO(0x45008), D_SKL | D_KBL);
2819 2819
2820 MMIO_D(0x46430, D_SKL | D_KBL); 2820 MMIO_D(_MMIO(0x46430), D_SKL | D_KBL);
2821 2821
2822 MMIO_D(0x46520, D_SKL | D_KBL); 2822 MMIO_D(_MMIO(0x46520), D_SKL | D_KBL);
2823 2823
2824 MMIO_D(0xc403c, D_SKL | D_KBL); 2824 MMIO_D(_MMIO(0xc403c), D_SKL | D_KBL);
2825 MMIO_D(0xb004, D_SKL_PLUS); 2825 MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
2826 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2826 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2827 2827
2828 MMIO_D(0x65900, D_SKL_PLUS); 2828 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
2829 MMIO_D(0x1082c0, D_SKL | D_KBL); 2829 MMIO_D(_MMIO(0x1082c0), D_SKL | D_KBL);
2830 MMIO_D(0x4068, D_SKL | D_KBL); 2830 MMIO_D(_MMIO(0x4068), D_SKL | D_KBL);
2831 MMIO_D(0x67054, D_SKL | D_KBL); 2831 MMIO_D(_MMIO(0x67054), D_SKL | D_KBL);
2832 MMIO_D(0x6e560, D_SKL | D_KBL); 2832 MMIO_D(_MMIO(0x6e560), D_SKL | D_KBL);
2833 MMIO_D(0x6e554, D_SKL | D_KBL); 2833 MMIO_D(_MMIO(0x6e554), D_SKL | D_KBL);
2834 MMIO_D(0x2b20, D_SKL | D_KBL); 2834 MMIO_D(_MMIO(0x2b20), D_SKL | D_KBL);
2835 MMIO_D(0x65f00, D_SKL | D_KBL); 2835 MMIO_D(_MMIO(0x65f00), D_SKL | D_KBL);
2836 MMIO_D(0x65f08, D_SKL | D_KBL); 2836 MMIO_D(_MMIO(0x65f08), D_SKL | D_KBL);
2837 MMIO_D(0x320f0, D_SKL | D_KBL); 2837 MMIO_D(_MMIO(0x320f0), D_SKL | D_KBL);
2838 2838
2839 MMIO_D(0x70034, D_SKL_PLUS); 2839 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
2840 MMIO_D(0x71034, D_SKL_PLUS); 2840 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
2841 MMIO_D(0x72034, D_SKL_PLUS); 2841 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
2842 2842
2843 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS); 2843 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
2844 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS); 2844 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
2845 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS); 2845 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
2846 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS); 2846 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
2847 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS); 2847 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
2848 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS); 2848 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
2849 2849
2850 MMIO_D(0x44500, D_SKL_PLUS); 2850 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
2851 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2851 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2852 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS, 2852 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
2853 NULL, NULL); 2853 NULL, NULL);
2854 2854
2855 MMIO_D(0x4ab8, D_KBL); 2855 MMIO_D(_MMIO(0x4ab8), D_KBL);
2856 MMIO_D(0x2248, D_SKL_PLUS | D_KBL); 2856 MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL);
2857 2857
2858 return 0; 2858 return 0;
2859} 2859}
@@ -2869,8 +2869,8 @@ static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2869 for (i = 0; i < num; i++, block++) { 2869 for (i = 0; i < num; i++, block++) {
2870 if (!(device & block->device)) 2870 if (!(device & block->device))
2871 continue; 2871 continue;
2872 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) && 2872 if (offset >= i915_mmio_reg_offset(block->offset) &&
2873 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size) 2873 offset < i915_mmio_reg_offset(block->offset) + block->size)
2874 return block; 2874 return block;
2875 } 2875 }
2876 return NULL; 2876 return NULL;
@@ -2982,8 +2982,8 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
2982 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 2982 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
2983 for (j = 0; j < block->size; j += 4) { 2983 for (j = 0; j < block->size; j += 4) {
2984 ret = handler(gvt, 2984 ret = handler(gvt,
2985 INTEL_GVT_MMIO_OFFSET(block->offset) + j, 2985 i915_mmio_reg_offset(block->offset) + j,
2986 data); 2986 data);
2987 if (ret) 2987 if (ret)
2988 return ret; 2988 return ret;
2989 } 2989 }
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index f86983d6655b..45bab5a6290b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1360,8 +1360,8 @@ static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa,
1360 struct kvmgt_guest_info, track_node); 1360 struct kvmgt_guest_info, track_node);
1361 1361
1362 if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) 1362 if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa)))
1363 intel_gvt_ops->emulate_mmio_write(info->vgpu, gpa, 1363 intel_gvt_ops->write_protect_handler(info->vgpu, gpa,
1364 (void *)val, len); 1364 (void *)val, len);
1365} 1365}
1366 1366
1367static void kvmgt_page_track_flush_slot(struct kvm *kvm, 1367static void kvmgt_page_track_flush_slot(struct kvm *kvm,
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index f7227a3ad469..562b5ad857a4 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -117,25 +117,6 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
117 else 117 else
118 memcpy(pt, p_data, bytes); 118 memcpy(pt, p_data, bytes);
119 119
120 } else if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) {
121 struct intel_vgpu_page_track *t;
122
123 /* Since we enter the failsafe mode early during guest boot,
124 * guest may not have chance to set up its ppgtt table, so
125 * there should not be any wp pages for guest. Keep the wp
126 * related code here in case we need to handle it in furture.
127 */
128 t = intel_vgpu_find_tracked_page(vgpu, pa >> PAGE_SHIFT);
129 if (t) {
130 /* remove write protection to prevent furture traps */
131 intel_vgpu_clean_page_track(vgpu, t);
132 if (read)
133 intel_gvt_hypervisor_read_gpa(vgpu, pa,
134 p_data, bytes);
135 else
136 intel_gvt_hypervisor_write_gpa(vgpu, pa,
137 p_data, bytes);
138 }
139 } 120 }
140 mutex_unlock(&gvt->lock); 121 mutex_unlock(&gvt->lock);
141} 122}
@@ -168,23 +149,6 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
168 goto out; 149 goto out;
169 } 150 }
170 151
171 if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) {
172 struct intel_vgpu_page_track *t;
173
174 t = intel_vgpu_find_tracked_page(vgpu, pa >> PAGE_SHIFT);
175 if (t) {
176 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa,
177 p_data, bytes);
178 if (ret) {
179 gvt_vgpu_err("guest page read error %d, "
180 "gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
181 ret, t->gfn, pa, *(u32 *)p_data,
182 bytes);
183 }
184 goto out;
185 }
186 }
187
188 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 152 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
189 153
190 if (WARN_ON(bytes > 8)) 154 if (WARN_ON(bytes > 8))
@@ -263,23 +227,6 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
263 goto out; 227 goto out;
264 } 228 }
265 229
266 if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) {
267 struct intel_vgpu_page_track *t;
268
269 t = intel_vgpu_find_tracked_page(vgpu, pa >> PAGE_SHIFT);
270 if (t) {
271 ret = t->handler(t, pa, p_data, bytes);
272 if (ret) {
273 gvt_err("guest page write error %d, "
274 "gfn 0x%lx, pa 0x%llx, "
275 "var 0x%x, len %d\n",
276 ret, t->gfn, pa,
277 *(u32 *)p_data, bytes);
278 }
279 goto out;
280 }
281 }
282
283 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 230 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
284 231
285 if (WARN_ON(bytes > 8)) 232 if (WARN_ON(bytes > 8))
@@ -336,10 +283,10 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
336 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size); 283 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
337 memcpy(vgpu->mmio.sreg, mmio, info->mmio_size); 284 memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
338 285
339 vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 286 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
340 287
341 /* set the bit 0:2(Core C-State ) to C0 */ 288 /* set the bit 0:2(Core C-State ) to C0 */
342 vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0; 289 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
343 290
344 vgpu->mmio.disable_warn_untrack = false; 291 vgpu->mmio.disable_warn_untrack = false;
345 } else { 292 } else {
diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h
index 62709ac351cd..71b620875943 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.h
+++ b/drivers/gpu/drm/i915/gvt/mmio.h
@@ -76,13 +76,6 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
76 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 76 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
77 void *data); 77 void *data);
78 78
79
80#define INTEL_GVT_MMIO_OFFSET(reg) ({ \
81 typeof(reg) __reg = reg; \
82 u32 *offset = (u32 *)&__reg; \
83 *offset; \
84})
85
86int intel_vgpu_init_mmio(struct intel_vgpu *vgpu); 79int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
87void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr); 80void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
88void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu); 81void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 8a52b56f0e86..74834395dd89 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -149,8 +149,41 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
149 { /* Terminated */ } 149 { /* Terminated */ }
150}; 150};
151 151
152static u32 gen9_render_mocs[I915_NUM_ENGINES][64]; 152static struct {
153static u32 gen9_render_mocs_L3[32]; 153 bool initialized;
154 u32 control_table[I915_NUM_ENGINES][64];
155 u32 l3cc_table[32];
156} gen9_render_mocs;
157
158static void load_render_mocs(struct drm_i915_private *dev_priv)
159{
160 i915_reg_t offset;
161 u32 regs[] = {
162 [RCS] = 0xc800,
163 [VCS] = 0xc900,
164 [VCS2] = 0xca00,
165 [BCS] = 0xcc00,
166 [VECS] = 0xcb00,
167 };
168 int ring_id, i;
169
170 for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
171 offset.reg = regs[ring_id];
172 for (i = 0; i < 64; i++) {
173 gen9_render_mocs.control_table[ring_id][i] =
174 I915_READ_FW(offset);
175 offset.reg += 4;
176 }
177 }
178
179 offset.reg = 0xb020;
180 for (i = 0; i < 32; i++) {
181 gen9_render_mocs.l3cc_table[i] =
182 I915_READ_FW(offset);
183 offset.reg += 4;
184 }
185 gen9_render_mocs.initialized = true;
186}
154 187
155static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 188static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
156{ 189{
@@ -191,17 +224,20 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
191 if (wait_for_atomic((I915_READ_FW(reg) == 0), 50)) 224 if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
192 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id); 225 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
193 else 226 else
194 vgpu_vreg(vgpu, regs[ring_id]) = 0; 227 vgpu_vreg_t(vgpu, reg) = 0;
195 228
196 intel_uncore_forcewake_put(dev_priv, fw); 229 intel_uncore_forcewake_put(dev_priv, fw);
197 230
198 gvt_dbg_core("invalidate TLB for ring %d\n", ring_id); 231 gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
199} 232}
200 233
201static void load_mocs(struct intel_vgpu *vgpu, int ring_id) 234static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
235 int ring_id)
202{ 236{
203 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 237 struct drm_i915_private *dev_priv;
204 i915_reg_t offset, l3_offset; 238 i915_reg_t offset, l3_offset;
239 u32 old_v, new_v;
240
205 u32 regs[] = { 241 u32 regs[] = {
206 [RCS] = 0xc800, 242 [RCS] = 0xc800,
207 [VCS] = 0xc900, 243 [VCS] = 0xc900,
@@ -211,54 +247,45 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
211 }; 247 };
212 int i; 248 int i;
213 249
250 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
214 if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) 251 if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
215 return; 252 return;
216 253
254 if (!pre && !gen9_render_mocs.initialized)
255 load_render_mocs(dev_priv);
256
217 offset.reg = regs[ring_id]; 257 offset.reg = regs[ring_id];
218 for (i = 0; i < 64; i++) { 258 for (i = 0; i < 64; i++) {
219 gen9_render_mocs[ring_id][i] = I915_READ_FW(offset); 259 if (pre)
220 I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset)); 260 old_v = vgpu_vreg_t(pre, offset);
221 offset.reg += 4; 261 else
222 } 262 old_v = gen9_render_mocs.control_table[ring_id][i];
223 263 if (next)
224 if (ring_id == RCS) { 264 new_v = vgpu_vreg_t(next, offset);
225 l3_offset.reg = 0xb020; 265 else
226 for (i = 0; i < 32; i++) { 266 new_v = gen9_render_mocs.control_table[ring_id][i];
227 gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
228 I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
229 l3_offset.reg += 4;
230 }
231 }
232}
233 267
234static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) 268 if (old_v != new_v)
235{ 269 I915_WRITE_FW(offset, new_v);
236 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
237 i915_reg_t offset, l3_offset;
238 u32 regs[] = {
239 [RCS] = 0xc800,
240 [VCS] = 0xc900,
241 [VCS2] = 0xca00,
242 [BCS] = 0xcc00,
243 [VECS] = 0xcb00,
244 };
245 int i;
246 270
247 if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
248 return;
249
250 offset.reg = regs[ring_id];
251 for (i = 0; i < 64; i++) {
252 vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
253 I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
254 offset.reg += 4; 271 offset.reg += 4;
255 } 272 }
256 273
257 if (ring_id == RCS) { 274 if (ring_id == RCS) {
258 l3_offset.reg = 0xb020; 275 l3_offset.reg = 0xb020;
259 for (i = 0; i < 32; i++) { 276 for (i = 0; i < 32; i++) {
260 vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset); 277 if (pre)
261 I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]); 278 old_v = vgpu_vreg_t(pre, l3_offset);
279 else
280 old_v = gen9_render_mocs.l3cc_table[i];
281 if (next)
282 new_v = vgpu_vreg_t(next, l3_offset);
283 else
284 new_v = gen9_render_mocs.l3cc_table[i];
285
286 if (old_v != new_v)
287 I915_WRITE_FW(l3_offset, new_v);
288
262 l3_offset.reg += 4; 289 l3_offset.reg += 4;
263 } 290 }
264 } 291 }
@@ -266,84 +293,77 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
266 293
267#define CTX_CONTEXT_CONTROL_VAL 0x03 294#define CTX_CONTEXT_CONTROL_VAL 0x03
268 295
269/* Switch ring mmio values (context) from host to a vgpu. */ 296/* Switch ring mmio values (context). */
270static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) 297static void switch_mmio(struct intel_vgpu *pre,
298 struct intel_vgpu *next,
299 int ring_id)
271{ 300{
272 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 301 struct drm_i915_private *dev_priv;
273 struct intel_vgpu_submission *s = &vgpu->submission; 302 struct intel_vgpu_submission *s;
274 u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state; 303 u32 *reg_state, ctx_ctrl;
275 u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
276 u32 inhibit_mask = 304 u32 inhibit_mask =
277 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 305 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
278 struct engine_mmio *mmio; 306 struct engine_mmio *mmio;
279 u32 v; 307 u32 old_v, new_v;
280
281 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
282 load_mocs(vgpu, ring_id);
283
284 mmio = vgpu->gvt->engine_mmio_list;
285 while (i915_mmio_reg_offset((mmio++)->reg)) {
286 if (mmio->ring_id != ring_id)
287 continue;
288
289 mmio->value = I915_READ_FW(mmio->reg);
290
291 /*
292 * if it is an inhibit context, load in_context mmio
293 * into HW by mmio write. If it is not, skip this mmio
294 * write.
295 */
296 if (mmio->in_context &&
297 (ctx_ctrl & inhibit_mask) != inhibit_mask)
298 continue;
299
300 if (mmio->mask)
301 v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
302 else
303 v = vgpu_vreg(vgpu, mmio->reg);
304
305 I915_WRITE_FW(mmio->reg, v);
306
307 trace_render_mmio(vgpu->id, "load",
308 i915_mmio_reg_offset(mmio->reg),
309 mmio->value, v);
310 }
311
312 handle_tlb_pending_event(vgpu, ring_id);
313}
314
315/* Switch ring mmio values (context) from vgpu to host. */
316static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
317{
318 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
319 struct engine_mmio *mmio;
320 u32 v;
321 308
309 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
322 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 310 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
323 restore_mocs(vgpu, ring_id); 311 switch_mocs(pre, next, ring_id);
324 312
325 mmio = vgpu->gvt->engine_mmio_list; 313 mmio = dev_priv->gvt->engine_mmio_list;
326 while (i915_mmio_reg_offset((mmio++)->reg)) { 314 while (i915_mmio_reg_offset((mmio++)->reg)) {
327 if (mmio->ring_id != ring_id) 315 if (mmio->ring_id != ring_id)
328 continue; 316 continue;
329 317 // save
330 vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg); 318 if (pre) {
331 319 vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
332 if (mmio->mask) { 320 if (mmio->mask)
333 vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16); 321 vgpu_vreg_t(pre, mmio->reg) &=
334 v = mmio->value | (mmio->mask << 16); 322 ~(mmio->mask << 16);
323 old_v = vgpu_vreg_t(pre, mmio->reg);
335 } else 324 } else
336 v = mmio->value; 325 old_v = mmio->value = I915_READ_FW(mmio->reg);
337 326
338 if (mmio->in_context) 327 // restore
339 continue; 328 if (next) {
329 s = &next->submission;
330 reg_state =
331 s->shadow_ctx->engine[ring_id].lrc_reg_state;
332 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
333 /*
334 * if it is an inhibit context, load in_context mmio
335 * into HW by mmio write. If it is not, skip this mmio
336 * write.
337 */
338 if (mmio->in_context &&
339 (ctx_ctrl & inhibit_mask) != inhibit_mask)
340 continue;
341
342 if (mmio->mask)
343 new_v = vgpu_vreg_t(next, mmio->reg) |
344 (mmio->mask << 16);
345 else
346 new_v = vgpu_vreg_t(next, mmio->reg);
347 } else {
348 if (mmio->in_context)
349 continue;
350 if (mmio->mask)
351 new_v = mmio->value | (mmio->mask << 16);
352 else
353 new_v = mmio->value;
354 }
340 355
341 I915_WRITE_FW(mmio->reg, v); 356 I915_WRITE_FW(mmio->reg, new_v);
342 357
343 trace_render_mmio(vgpu->id, "restore", 358 trace_render_mmio(pre ? pre->id : 0,
359 next ? next->id : 0,
360 "switch",
344 i915_mmio_reg_offset(mmio->reg), 361 i915_mmio_reg_offset(mmio->reg),
345 mmio->value, v); 362 old_v, new_v);
346 } 363 }
364
365 if (next)
366 handle_tlb_pending_event(next, ring_id);
347} 367}
348 368
349/** 369/**
@@ -374,17 +394,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
374 * handle forcewake mannually. 394 * handle forcewake mannually.
375 */ 395 */
376 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 396 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
377 397 switch_mmio(pre, next, ring_id);
378 /**
379 * TODO: Optimize for vGPU to vGPU switch by merging
380 * switch_mmio_to_host() and switch_mmio_to_vgpu().
381 */
382 if (pre)
383 switch_mmio_to_host(pre, ring_id);
384
385 if (next)
386 switch_mmio_to_vgpu(next, ring_id);
387
388 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 398 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
389} 399}
390 400
diff --git a/drivers/gpu/drm/i915/gvt/trace.h b/drivers/gpu/drm/i915/gvt/trace.h
index 8c150381d9a4..7a2511538f34 100644
--- a/drivers/gpu/drm/i915/gvt/trace.h
+++ b/drivers/gpu/drm/i915/gvt/trace.h
@@ -330,13 +330,14 @@ TRACE_EVENT(inject_msi,
330); 330);
331 331
332TRACE_EVENT(render_mmio, 332TRACE_EVENT(render_mmio,
333 TP_PROTO(int id, char *action, unsigned int reg, 333 TP_PROTO(int old_id, int new_id, char *action, unsigned int reg,
334 unsigned int old_val, unsigned int new_val), 334 unsigned int old_val, unsigned int new_val),
335 335
336 TP_ARGS(id, action, reg, new_val, old_val), 336 TP_ARGS(old_id, new_id, action, reg, new_val, old_val),
337 337
338 TP_STRUCT__entry( 338 TP_STRUCT__entry(
339 __field(int, id) 339 __field(int, old_id)
340 __field(int, new_id)
340 __array(char, buf, GVT_TEMP_STR_LEN) 341 __array(char, buf, GVT_TEMP_STR_LEN)
341 __field(unsigned int, reg) 342 __field(unsigned int, reg)
342 __field(unsigned int, old_val) 343 __field(unsigned int, old_val)
@@ -344,15 +345,17 @@ TRACE_EVENT(render_mmio,
344 ), 345 ),
345 346
346 TP_fast_assign( 347 TP_fast_assign(
347 __entry->id = id; 348 __entry->old_id = old_id;
349 __entry->new_id = new_id;
348 snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", action); 350 snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", action);
349 __entry->reg = reg; 351 __entry->reg = reg;
350 __entry->old_val = old_val; 352 __entry->old_val = old_val;
351 __entry->new_val = new_val; 353 __entry->new_val = new_val;
352 ), 354 ),
353 355
354 TP_printk("VM%u %s reg %x, old %08x new %08x\n", 356 TP_printk("VM%u -> VM%u %s reg %x, old %08x new %08x\n",
355 __entry->id, __entry->buf, __entry->reg, 357 __entry->old_id, __entry->new_id,
358 __entry->buf, __entry->reg,
356 __entry->old_val, __entry->new_val) 359 __entry->old_val, __entry->new_val)
357); 360);
358 361
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 39926176fbeb..4688619f6a1c 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -38,25 +38,25 @@
38void populate_pvinfo_page(struct intel_vgpu *vgpu) 38void populate_pvinfo_page(struct intel_vgpu *vgpu)
39{ 39{
40 /* setup the ballooning information */ 40 /* setup the ballooning information */
41 vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC; 41 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
42 vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1; 42 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
43 vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; 43 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
44 vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; 44 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
45 vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; 45 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
46 46
47 vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT; 47 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
48 vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION; 48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
49 49
50 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 50 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
51 vgpu_aperture_gmadr_base(vgpu); 51 vgpu_aperture_gmadr_base(vgpu);
52 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = 52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
53 vgpu_aperture_sz(vgpu); 53 vgpu_aperture_sz(vgpu);
54 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
55 vgpu_hidden_gmadr_base(vgpu); 55 vgpu_hidden_gmadr_base(vgpu);
56 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = 56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
57 vgpu_hidden_sz(vgpu); 57 vgpu_hidden_sz(vgpu);
58 58
59 vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); 59 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
60 60
61 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); 61 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
62 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", 62 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 22:50:05 -0400