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authorDave Airlie <airlied@redhat.com>2015-10-22 21:54:03 -0400
committerDave Airlie <airlied@redhat.com>2015-10-22 21:54:03 -0400
commitd7e1bc3f5e70c5a106606e33cfa4d413459611ba (patch)
tree8a29a475c6d91ceb8e5785012072eeb8589ef05f /drivers
parent2b5f900e4fb18d85fc62d4efcf4e7016fc384806 (diff)
parenta9ee34b70e07ce942806eda154e48ea3f754a76f (diff)
Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next
A bit smaller pull this time. Few minor things, plus initial support for msm8996 (snapdragon 820).. Sorry, a bit latish, was hoping to get some 8960/8064 DSI stuff included. But still waiting on the v2 of the patchset (just pending some minor review comments). It would be nice to get the DSI patches merged since it would help some folks trying to get upstream kernel running on n4/n7 and xperia z and wanting to write some more panel drivers. Also, waiting for OCMEM driver to get merged via other trees and then I have a small bit to go along with that to make the gpu actually work on devices w/ OCMEM (snapdragon 800, 805, etc). So maybe a second later pull req, time permitting. * 'msm-next' of git://people.freedesktop.org/~robclark/linux: drm/msm: Remove local fbdev emulation Kconfig option drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996) drm/msm/mdp: Add Software Pixel Extension support drm/msm/mdp5: Use the newly introduced enum mdp_component_type drm/msm/hdmi: Add basic HDMI support for msm8996 drm/msm/mdp5: Avoid printing error messages for optional clocks drm/msm: Fix IOMMU clean up path in case msm_iommu_new() fails drm/msm/mdp5: remove the cfg pointer from SMP struct drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY drm: msm: dsi: Don't attempt changing voltage of switches drm/msm: update generated headers
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/msm/Kconfig14
-rw-r--r--drivers/gpu/drm/msm/Makefile2
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx.xml.h9
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx.xml.h27
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx.xml.h15
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_common.xml.h13
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h9
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.xml.h238
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_host.c2
-rw-r--r--drivers/gpu/drm/msm/dsi/mmss_cc.xml.h8
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy.c2
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c6
-rw-r--r--drivers/gpu/drm/msm/dsi/sfpb.xml.h21
-rw-r--r--drivers/gpu/drm/msm/edp/edp.xml.h8
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.c17
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.xml.h8
-rw-r--r--drivers/gpu/drm/msm/hdmi/qfprom.xml.h8
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h8
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h86
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c95
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h11
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c46
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h2
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c201
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c8
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp_common.xml.h15
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp_kms.h6
-rw-r--r--drivers/gpu/drm/msm/msm_drv.c8
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.c8
29 files changed, 684 insertions, 217 deletions
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 8e6c7c638e24..84d3ec98e6b9 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -14,20 +14,6 @@ config DRM_MSM
14 help 14 help
15 DRM/KMS driver for MSM/snapdragon. 15 DRM/KMS driver for MSM/snapdragon.
16 16
17config DRM_MSM_FBDEV
18 bool "Enable legacy fbdev support for MSM modesetting driver"
19 depends on DRM_MSM
20 select DRM_KMS_FB_HELPER
21 select FB_SYS_FILLRECT
22 select FB_SYS_COPYAREA
23 select FB_SYS_IMAGEBLIT
24 select FB_SYS_FOPS
25 default y
26 help
27 Choose this option if you have a need for the legacy fbdev
28 support. Note that this support also provide the linux console
29 support on top of the MSM modesetting driver.
30
31config DRM_MSM_REGISTER_LOGGING 17config DRM_MSM_REGISTER_LOGGING
32 bool "MSM DRM register logging" 18 bool "MSM DRM register logging"
33 depends on DRM_MSM 19 depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 0a543eb5e5d7..1c90290be716 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -50,7 +50,7 @@ msm-y := \
50 msm_rd.o \ 50 msm_rd.o \
51 msm_ringbuffer.o 51 msm_ringbuffer.o
52 52
53msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o 53msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
54msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o 54msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
55 55
56msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ 56msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 0261f0d31612..9e2aceb4ffe6 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
18 19
19Copyright (C) 2013-2015 by the following authors: 20Copyright (C) 2013-2015 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 21- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index 48d133711487..97dc1c6ec107 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
18 19
19Copyright (C) 2013-2015 by the following authors: 20Copyright (C) 2013-2015 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 21- Rob Clark <robdclark@gmail.com> (robclark)
@@ -280,6 +281,8 @@ enum a3xx_rb_blend_opcode {
280enum a3xx_intp_mode { 281enum a3xx_intp_mode {
281 SMOOTH = 0, 282 SMOOTH = 0,
282 FLAT = 1, 283 FLAT = 1,
284 ZERO = 2,
285 ONE = 3,
283}; 286};
284 287
285enum a3xx_repl_mode { 288enum a3xx_repl_mode {
@@ -680,9 +683,16 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
680#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 683#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
681#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 684#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
682#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 685#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
686#define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
683#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 687#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000
684#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 688#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000
685#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 689#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000
690#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000
691#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26
692static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
693{
694 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
695}
686 696
687#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 697#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
688#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 698#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
@@ -773,7 +783,7 @@ static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
773#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 783#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
774static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 784static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
775{ 785{
776 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 786 return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
777} 787}
778 788
779#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 789#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
@@ -894,6 +904,9 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
894#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 904#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
895 905
896#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 906#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
907#define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001
908#define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002
909#define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004
897#define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 910#define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008
898#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 911#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
899#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 912#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
@@ -907,6 +920,8 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
907#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 920#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
908#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 921#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
909#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 922#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
923#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000
924#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000
910#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 925#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
911#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 926#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
912#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 927#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
@@ -914,6 +929,8 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compar
914{ 929{
915 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 930 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
916} 931}
932#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000
933#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000
917 934
918#define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 935#define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
919#define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 936#define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
index ac55066db3b0..99de8271dba8 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
18 19
19Copyright (C) 2013-2015 by the following authors: 20Copyright (C) 2013-2015 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 21- Rob Clark <robdclark@gmail.com> (robclark)
@@ -162,10 +163,13 @@ enum a4xx_tex_fmt {
162 TFMT4_8_UNORM = 4, 163 TFMT4_8_UNORM = 4,
163 TFMT4_8_8_UNORM = 14, 164 TFMT4_8_8_UNORM = 14,
164 TFMT4_8_8_8_8_UNORM = 28, 165 TFMT4_8_8_8_8_UNORM = 28,
166 TFMT4_8_SNORM = 5,
165 TFMT4_8_8_SNORM = 15, 167 TFMT4_8_8_SNORM = 15,
166 TFMT4_8_8_8_8_SNORM = 29, 168 TFMT4_8_8_8_8_SNORM = 29,
169 TFMT4_8_UINT = 6,
167 TFMT4_8_8_UINT = 16, 170 TFMT4_8_8_UINT = 16,
168 TFMT4_8_8_8_8_UINT = 30, 171 TFMT4_8_8_8_8_UINT = 30,
172 TFMT4_8_SINT = 7,
169 TFMT4_8_8_SINT = 17, 173 TFMT4_8_8_SINT = 17,
170 TFMT4_8_8_8_8_SINT = 31, 174 TFMT4_8_8_8_8_SINT = 31,
171 TFMT4_16_UINT = 21, 175 TFMT4_16_UINT = 21,
@@ -246,7 +250,8 @@ enum a4xx_tex_clamp {
246 A4XX_TEX_REPEAT = 0, 250 A4XX_TEX_REPEAT = 0,
247 A4XX_TEX_CLAMP_TO_EDGE = 1, 251 A4XX_TEX_CLAMP_TO_EDGE = 1,
248 A4XX_TEX_MIRROR_REPEAT = 2, 252 A4XX_TEX_MIRROR_REPEAT = 2,
249 A4XX_TEX_CLAMP_NONE = 3, 253 A4XX_TEX_CLAMP_TO_BORDER = 3,
254 A4XX_TEX_MIRROR_CLAMP = 4,
250}; 255};
251 256
252enum a4xx_tex_aniso { 257enum a4xx_tex_aniso {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index 399a9e528139..c304468cf2bd 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
18 19
19Copyright (C) 2013-2015 by the following authors: 20Copyright (C) 2013-2015 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 21- Rob Clark <robdclark@gmail.com> (robclark)
@@ -85,6 +86,10 @@ enum adreno_rb_blend_factor {
85 FACTOR_CONSTANT_ALPHA = 14, 86 FACTOR_CONSTANT_ALPHA = 14,
86 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 87 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
87 FACTOR_SRC_ALPHA_SATURATE = 16, 88 FACTOR_SRC_ALPHA_SATURATE = 16,
89 FACTOR_SRC1_COLOR = 20,
90 FACTOR_ONE_MINUS_SRC1_COLOR = 21,
91 FACTOR_SRC1_ALPHA = 22,
92 FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
88}; 93};
89 94
90enum adreno_rb_surface_endian { 95enum adreno_rb_surface_endian {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index 41904fed1350..a22fef569499 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
18 19
19Copyright (C) 2013-2015 by the following authors: 20Copyright (C) 2013-2015 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 21- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 1d2e32f0817b..b2b5f3dd1b4c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
@@ -567,114 +567,234 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
567#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc 567#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
568#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 568#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
569 569
570static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; } 570static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
571 571
572static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; } 572static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
573 573
574static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; } 574static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
575 575
576static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; } 576static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
577 577
578static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; } 578static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
579 579
580static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; } 580static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
581 581
582static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; } 582static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
583 583
584#define REG_DSI_8960_PHY_LNCK_CFG_0 0x00000400 584#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
585 585
586#define REG_DSI_8960_PHY_LNCK_CFG_1 0x00000404 586#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
587 587
588#define REG_DSI_8960_PHY_LNCK_CFG_2 0x00000408 588#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
589 589
590#define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH 0x0000040c 590#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
591 591
592#define REG_DSI_8960_PHY_LNCK_TEST_STR0 0x00000414 592#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
593 593
594#define REG_DSI_8960_PHY_LNCK_TEST_STR1 0x00000418 594#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
595 595
596#define REG_DSI_8960_PHY_TIMING_CTRL_0 0x00000440 596#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
597#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
598#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
599static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
600{
601 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
602}
603
604#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
605#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
606#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
607static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
608{
609 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
610}
611
612#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
613#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
614#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
615static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
616{
617 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
618}
619
620#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
621
622#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
623#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
624#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
625static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
626{
627 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
628}
629
630#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
631#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
632#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
633static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
634{
635 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
636}
637
638#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
639#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
640#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
641static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
642{
643 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
644}
645
646#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
647#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
648#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
649static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
650{
651 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
652}
653
654#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
655#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
656#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
657static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
658{
659 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
660}
661
662#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
663#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
664#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
665static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
666{
667 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
668}
669#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
670#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
671static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
672{
673 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
674}
675
676#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
677#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
678#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
679static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
680{
681 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
682}
683
684#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
685#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
686#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
687static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
688{
689 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
690}
691
692#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
693
694#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
695
696#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
697
698#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
699
700#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
701
702#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
703
704#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
705
706#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
707
708#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
709
710#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
711
712#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
713
714#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
597 715
598#define REG_DSI_8960_PHY_TIMING_CTRL_1 0x00000444 716#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
599 717
600#define REG_DSI_8960_PHY_TIMING_CTRL_2 0x00000448 718#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
601 719
602#define REG_DSI_8960_PHY_TIMING_CTRL_3 0x0000044c 720#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
603 721
604#define REG_DSI_8960_PHY_TIMING_CTRL_4 0x00000450 722#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
605 723
606#define REG_DSI_8960_PHY_TIMING_CTRL_5 0x00000454 724#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
607 725
608#define REG_DSI_8960_PHY_TIMING_CTRL_6 0x00000458 726#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
609 727
610#define REG_DSI_8960_PHY_TIMING_CTRL_7 0x0000045c 728#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
611 729
612#define REG_DSI_8960_PHY_TIMING_CTRL_8 0x00000460 730#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
613 731
614#define REG_DSI_8960_PHY_TIMING_CTRL_9 0x00000464 732#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
615 733
616#define REG_DSI_8960_PHY_TIMING_CTRL_10 0x00000468 734#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
617 735
618#define REG_DSI_8960_PHY_TIMING_CTRL_11 0x0000046c 736#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
619 737
620#define REG_DSI_8960_PHY_CTRL_0 0x00000470 738#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
621 739
622#define REG_DSI_8960_PHY_CTRL_1 0x00000474 740#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
623 741
624#define REG_DSI_8960_PHY_CTRL_2 0x00000478 742#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
625 743
626#define REG_DSI_8960_PHY_CTRL_3 0x0000047c 744#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
627 745
628#define REG_DSI_8960_PHY_STRENGTH_0 0x00000480 746#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
629 747
630#define REG_DSI_8960_PHY_STRENGTH_1 0x00000484 748#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
631 749
632#define REG_DSI_8960_PHY_STRENGTH_2 0x00000488 750#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
751#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
633 752
634#define REG_DSI_8960_PHY_BIST_CTRL_0 0x0000048c 753#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
754#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
635 755
636#define REG_DSI_8960_PHY_BIST_CTRL_1 0x00000490 756#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
637 757
638#define REG_DSI_8960_PHY_BIST_CTRL_2 0x00000494 758#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
639 759
640#define REG_DSI_8960_PHY_BIST_CTRL_3 0x00000498 760#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
641 761
642#define REG_DSI_8960_PHY_BIST_CTRL_4 0x0000049c 762#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
643 763
644#define REG_DSI_8960_PHY_LDO_CTRL 0x000004b0 764#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
645 765
646#define REG_DSI_8960_PHY_REGULATOR_CTRL_0 0x00000500 766#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
647 767
648#define REG_DSI_8960_PHY_REGULATOR_CTRL_1 0x00000504 768#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
649 769
650#define REG_DSI_8960_PHY_REGULATOR_CTRL_2 0x00000508 770#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
651 771
652#define REG_DSI_8960_PHY_REGULATOR_CTRL_3 0x0000050c 772#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
653 773
654#define REG_DSI_8960_PHY_REGULATOR_CTRL_4 0x00000510 774#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
655 775
656#define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG 0x00000518 776#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
657 777
658#define REG_DSI_8960_PHY_CAL_HW_TRIGGER 0x00000528 778#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
659 779
660#define REG_DSI_8960_PHY_CAL_SW_CFG_0 0x0000052c 780#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
661 781
662#define REG_DSI_8960_PHY_CAL_SW_CFG_1 0x00000530 782#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
663 783
664#define REG_DSI_8960_PHY_CAL_SW_CFG_2 0x00000534 784#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
665 785
666#define REG_DSI_8960_PHY_CAL_HW_CFG_0 0x00000538 786#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
667 787
668#define REG_DSI_8960_PHY_CAL_HW_CFG_1 0x0000053c 788#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
669 789
670#define REG_DSI_8960_PHY_CAL_HW_CFG_2 0x00000540 790#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
671 791
672#define REG_DSI_8960_PHY_CAL_HW_CFG_3 0x00000544 792#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
673 793
674#define REG_DSI_8960_PHY_CAL_HW_CFG_4 0x00000548 794#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
675 795
676#define REG_DSI_8960_PHY_CAL_STATUS 0x00000550 796#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
677#define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010 797#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
678 798
679static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 799static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
680 800
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 8d82973fe9db..4c49868efcda 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -278,7 +278,7 @@ static int dsi_regulator_init(struct msm_dsi_host *msm_host)
278 } 278 }
279 279
280 for (i = 0; i < num; i++) { 280 for (i = 0; i < num; i++) {
281 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { 281 if (regulator_can_change_voltage(s[i].consumer)) {
282 ret = regulator_set_voltage(s[i].consumer, 282 ret = regulator_set_voltage(s[i].consumer,
283 regs[i].min_voltage, regs[i].max_voltage); 283 regs[i].min_voltage, regs[i].max_voltage);
284 if (ret < 0) { 284 if (ret < 0) {
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
index 5de505e627be..80ec65e47468 100644
--- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 401ff58d6893..f1f955f571fa 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -178,7 +178,7 @@ static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
178 } 178 }
179 179
180 for (i = 0; i < num; i++) { 180 for (i = 0; i < num; i++) {
181 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { 181 if (regulator_can_change_voltage(s[i].consumer)) {
182 ret = regulator_set_voltage(s[i].consumer, 182 ret = regulator_set_voltage(s[i].consumer,
183 regs[i].min_voltage, regs[i].max_voltage); 183 regs[i].min_voltage, regs[i].max_voltage);
184 if (ret < 0) { 184 if (ret < 0) {
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index f1a7c7b46420..edf74110ced7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -99,16 +99,14 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
99 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); 99 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
100 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); 100 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
101 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); 101 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
102 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0);
102 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); 103 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
103 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); 104 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
104 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); 105 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
105 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); 106 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
106 } 107 }
107 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0);
108 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5);
109 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa);
110 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf);
111 108
109 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0);
112 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); 110 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
113 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); 111 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
114 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); 112 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
index 06cbddfc914f..7d7662e69e11 100644
--- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
+++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
@@ -45,7 +45,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
45*/ 45*/
46 46
47 47
48#define REG_SFPB_CFG 0x00000058 48enum sfpb_ahb_arb_master_port_en {
49 SFPB_MASTER_PORT_ENABLE = 3,
50 SFPB_MASTER_PORT_DISABLE = 0,
51};
52
53#define REG_SFPB_GPREG 0x00000058
54#define SFPB_GPREG_MASTER_PORT_EN__MASK 0x00001800
55#define SFPB_GPREG_MASTER_PORT_EN__SHIFT 11
56static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val)
57{
58 return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK;
59}
49 60
50 61
51#endif /* SFPB_XML */ 62#endif /* SFPB_XML */
diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h
index bef1d65fe28c..90bf5ed46746 100644
--- a/drivers/gpu/drm/msm/edp/edp.xml.h
+++ b/drivers/gpu/drm/msm/edp/edp.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 101b324cdeef..1f4a95eeb348 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -328,6 +328,9 @@ fail:
328 .item ## _names = item ##_names_ ## entry, \ 328 .item ## _names = item ##_names_ ## entry, \
329 .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry) 329 .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry)
330 330
331static const char *pwr_reg_names_none[] = {};
332static const char *hpd_reg_names_none[] = {};
333
331static struct hdmi_platform_config hdmi_tx_8660_config = { 334static struct hdmi_platform_config hdmi_tx_8660_config = {
332 .phy_init = hdmi_phy_8x60_init, 335 .phy_init = hdmi_phy_8x60_init,
333}; 336};
@@ -367,18 +370,26 @@ static struct hdmi_platform_config hdmi_tx_8084_config = {
367 .hpd_freq = hpd_clk_freq_8x74, 370 .hpd_freq = hpd_clk_freq_8x74,
368}; 371};
369 372
370static const char *hpd_reg_names_8x94[] = {};
371
372static struct hdmi_platform_config hdmi_tx_8994_config = { 373static struct hdmi_platform_config hdmi_tx_8994_config = {
373 .phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */ 374 .phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */
374 HDMI_CFG(pwr_reg, 8x74), 375 HDMI_CFG(pwr_reg, 8x74),
375 HDMI_CFG(hpd_reg, 8x94), 376 HDMI_CFG(hpd_reg, none),
377 HDMI_CFG(pwr_clk, 8x74),
378 HDMI_CFG(hpd_clk, 8x74),
379 .hpd_freq = hpd_clk_freq_8x74,
380};
381
382static struct hdmi_platform_config hdmi_tx_8996_config = {
383 .phy_init = NULL,
384 HDMI_CFG(pwr_reg, none),
385 HDMI_CFG(hpd_reg, none),
376 HDMI_CFG(pwr_clk, 8x74), 386 HDMI_CFG(pwr_clk, 8x74),
377 HDMI_CFG(hpd_clk, 8x74), 387 HDMI_CFG(hpd_clk, 8x74),
378 .hpd_freq = hpd_clk_freq_8x74, 388 .hpd_freq = hpd_clk_freq_8x74,
379}; 389};
380 390
381static const struct of_device_id dt_match[] = { 391static const struct of_device_id dt_match[] = {
392 { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config },
382 { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config }, 393 { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config },
383 { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config }, 394 { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config },
384 { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config }, 395 { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config },
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 0b1b5586ff35..10c45700aefe 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
index 2aa23b98f8aa..dbd9cc4daf2e 100644
--- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index 74b86734fef5..d5d94575fa1b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index 3469f50d5590..c37da9c61e29 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
@@ -895,6 +895,7 @@ static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
895#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000 895#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
896#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000 896#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
897#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000 897#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
898#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
898 899
899static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); } 900static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
900 901
@@ -932,6 +933,83 @@ static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
932 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; 933 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
933} 934}
934 935
936static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
937{
938 switch (idx) {
939 case COMP_0: return 0x00000100;
940 case COMP_1_2: return 0x00000110;
941 case COMP_3: return 0x00000120;
942 default: return INVALID_IDX(idx);
943 }
944}
945static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
946
947static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
948#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
949#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
950static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
951{
952 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
953}
954#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
955#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
956static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
957{
958 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
959}
960#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
961#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
962static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
963{
964 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
965}
966#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
967#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
968static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
969{
970 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
971}
972
973static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
974#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
975#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
976static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
977{
978 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
979}
980#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
981#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
982static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
983{
984 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
985}
986#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
987#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
988static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
989{
990 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
991}
992#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
993#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
994static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
995{
996 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
997}
998
999static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
1000#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
1001#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
1002static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1003{
1004 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1005}
1006#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
1007#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
1008static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1009{
1010 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1011}
1012
935static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); } 1013static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
936#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001 1014#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
937#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002 1015#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index a1e26f23c7cc..bb1225aa2f75 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -27,6 +27,8 @@ const struct mdp5_cfg_hw msm8x74v1_config = {
27 .mdp = { 27 .mdp = {
28 .count = 1, 28 .count = 1,
29 .base = { 0x00100 }, 29 .base = { 0x00100 },
30 .caps = MDP_CAP_SMP |
31 0,
30 }, 32 },
31 .smp = { 33 .smp = {
32 .mmb_count = 22, 34 .mmb_count = 22,
@@ -96,6 +98,8 @@ const struct mdp5_cfg_hw msm8x74v2_config = {
96 .mdp = { 98 .mdp = {
97 .count = 1, 99 .count = 1,
98 .base = { 0x00100 }, 100 .base = { 0x00100 },
101 .caps = MDP_CAP_SMP |
102 0,
99 }, 103 },
100 .smp = { 104 .smp = {
101 .mmb_count = 22, 105 .mmb_count = 22,
@@ -165,6 +169,8 @@ const struct mdp5_cfg_hw apq8084_config = {
165 .mdp = { 169 .mdp = {
166 .count = 1, 170 .count = 1,
167 .base = { 0x00100 }, 171 .base = { 0x00100 },
172 .caps = MDP_CAP_SMP |
173 0,
168 }, 174 },
169 .smp = { 175 .smp = {
170 .mmb_count = 44, 176 .mmb_count = 44,
@@ -242,6 +248,8 @@ const struct mdp5_cfg_hw msm8x16_config = {
242 .mdp = { 248 .mdp = {
243 .count = 1, 249 .count = 1,
244 .base = { 0x01000 }, 250 .base = { 0x01000 },
251 .caps = MDP_CAP_SMP |
252 0,
245 }, 253 },
246 .smp = { 254 .smp = {
247 .mmb_count = 8, 255 .mmb_count = 8,
@@ -301,6 +309,8 @@ const struct mdp5_cfg_hw msm8x94_config = {
301 .mdp = { 309 .mdp = {
302 .count = 1, 310 .count = 1,
303 .base = { 0x01000 }, 311 .base = { 0x01000 },
312 .caps = MDP_CAP_SMP |
313 0,
304 }, 314 },
305 .smp = { 315 .smp = {
306 .mmb_count = 44, 316 .mmb_count = 44,
@@ -370,7 +380,89 @@ const struct mdp5_cfg_hw msm8x94_config = {
370 [3] = INTF_HDMI, 380 [3] = INTF_HDMI,
371 }, 381 },
372 }, 382 },
373 .max_clk = 320000000, 383 .max_clk = 400000000,
384};
385
386const struct mdp5_cfg_hw msm8x96_config = {
387 .name = "msm8x96",
388 .mdp = {
389 .count = 1,
390 .base = { 0x01000 },
391 .caps = MDP_CAP_DSC |
392 MDP_CAP_CDM |
393 0,
394 },
395 .ctl = {
396 .count = 5,
397 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
398 .flush_hw_mask = 0xf4ffffff,
399 },
400 .pipe_vig = {
401 .count = 4,
402 .base = { 0x05000, 0x07000, 0x09000, 0x0b000 },
403 .caps = MDP_PIPE_CAP_HFLIP |
404 MDP_PIPE_CAP_VFLIP |
405 MDP_PIPE_CAP_SCALE |
406 MDP_PIPE_CAP_CSC |
407 MDP_PIPE_CAP_DECIMATION |
408 MDP_PIPE_CAP_SW_PIX_EXT |
409 0,
410 },
411 .pipe_rgb = {
412 .count = 4,
413 .base = { 0x15000, 0x17000, 0x19000, 0x1b000 },
414 .caps = MDP_PIPE_CAP_HFLIP |
415 MDP_PIPE_CAP_VFLIP |
416 MDP_PIPE_CAP_SCALE |
417 MDP_PIPE_CAP_DECIMATION |
418 MDP_PIPE_CAP_SW_PIX_EXT |
419 0,
420 },
421 .pipe_dma = {
422 .count = 2,
423 .base = { 0x25000, 0x27000 },
424 .caps = MDP_PIPE_CAP_HFLIP |
425 MDP_PIPE_CAP_VFLIP |
426 MDP_PIPE_CAP_SW_PIX_EXT |
427 0,
428 },
429 .lm = {
430 .count = 6,
431 .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 },
432 .nb_stages = 8,
433 .max_width = 2560,
434 .max_height = 0xFFFF,
435 },
436 .dspp = {
437 .count = 2,
438 .base = { 0x55000, 0x57000 },
439 },
440 .ad = {
441 .count = 3,
442 .base = { 0x79000, 0x79800, 0x7a000 },
443 },
444 .pp = {
445 .count = 4,
446 .base = { 0x71000, 0x71800, 0x72000, 0x72800 },
447 },
448 .cdm = {
449 .count = 1,
450 .base = { 0x7a200 },
451 },
452 .dsc = {
453 .count = 2,
454 .base = { 0x81000, 0x81400 },
455 },
456 .intf = {
457 .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 },
458 .connect = {
459 [0] = INTF_DISABLED,
460 [1] = INTF_DSI,
461 [2] = INTF_DSI,
462 [3] = INTF_HDMI,
463 },
464 },
465 .max_clk = 412500000,
374}; 466};
375 467
376static const struct mdp5_cfg_handler cfg_handlers[] = { 468static const struct mdp5_cfg_handler cfg_handlers[] = {
@@ -379,6 +471,7 @@ static const struct mdp5_cfg_handler cfg_handlers[] = {
379 { .revision = 3, .config = { .hw = &apq8084_config } }, 471 { .revision = 3, .config = { .hw = &apq8084_config } },
380 { .revision = 6, .config = { .hw = &msm8x16_config } }, 472 { .revision = 6, .config = { .hw = &msm8x16_config } },
381 { .revision = 9, .config = { .hw = &msm8x94_config } }, 473 { .revision = 9, .config = { .hw = &msm8x94_config } },
474 { .revision = 7, .config = { .hw = &msm8x96_config } },
382}; 475};
383 476
384static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev); 477static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index efb918d9f68b..050e1618c836 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -61,7 +61,12 @@ struct mdp5_smp_block {
61 int mmb_size; /* MMB: size in bytes */ 61 int mmb_size; /* MMB: size in bytes */
62 uint32_t clients[MAX_CLIENTS]; /* SMP port allocation /pipe */ 62 uint32_t clients[MAX_CLIENTS]; /* SMP port allocation /pipe */
63 mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */ 63 mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
64 int reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */ 64 uint8_t reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */
65};
66
67struct mdp5_mdp_block {
68 MDP5_SUB_BLOCK_DEFINITION;
69 uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */
65}; 70};
66 71
67#define MDP5_INTF_NUM_MAX 5 72#define MDP5_INTF_NUM_MAX 5
@@ -74,7 +79,7 @@ struct mdp5_intf_block {
74struct mdp5_cfg_hw { 79struct mdp5_cfg_hw {
75 char *name; 80 char *name;
76 81
77 struct mdp5_sub_block mdp; 82 struct mdp5_mdp_block mdp;
78 struct mdp5_smp_block smp; 83 struct mdp5_smp_block smp;
79 struct mdp5_ctl_block ctl; 84 struct mdp5_ctl_block ctl;
80 struct mdp5_pipe_block pipe_vig; 85 struct mdp5_pipe_block pipe_vig;
@@ -84,6 +89,8 @@ struct mdp5_cfg_hw {
84 struct mdp5_sub_block dspp; 89 struct mdp5_sub_block dspp;
85 struct mdp5_sub_block ad; 90 struct mdp5_sub_block ad;
86 struct mdp5_sub_block pp; 91 struct mdp5_sub_block pp;
92 struct mdp5_sub_block dsc;
93 struct mdp5_sub_block cdm;
87 struct mdp5_intf_block intf; 94 struct mdp5_intf_block intf;
88 95
89 uint32_t max_clk; 96 uint32_t max_clk;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 047cb0433ccb..b532faa8026d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -452,15 +452,19 @@ static void read_hw_revision(struct mdp5_kms *mdp5_kms,
452} 452}
453 453
454static int get_clk(struct platform_device *pdev, struct clk **clkp, 454static int get_clk(struct platform_device *pdev, struct clk **clkp,
455 const char *name) 455 const char *name, bool mandatory)
456{ 456{
457 struct device *dev = &pdev->dev; 457 struct device *dev = &pdev->dev;
458 struct clk *clk = devm_clk_get(dev, name); 458 struct clk *clk = devm_clk_get(dev, name);
459 if (IS_ERR(clk)) { 459 if (IS_ERR(clk) && mandatory) {
460 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 460 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
461 return PTR_ERR(clk); 461 return PTR_ERR(clk);
462 } 462 }
463 *clkp = clk; 463 if (IS_ERR(clk))
464 DBG("skipping %s", name);
465 else
466 *clkp = clk;
467
464 return 0; 468 return 0;
465} 469}
466 470
@@ -514,25 +518,26 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
514 goto fail; 518 goto fail;
515 } 519 }
516 520
517 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk"); 521 /* mandatory clocks: */
522 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true);
518 if (ret) 523 if (ret)
519 goto fail; 524 goto fail;
520 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk"); 525 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);
521 if (ret) 526 if (ret)
522 goto fail; 527 goto fail;
523 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src"); 528 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true);
524 if (ret) 529 if (ret)
525 goto fail; 530 goto fail;
526 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk"); 531 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
527 if (ret) 532 if (ret)
528 goto fail; 533 goto fail;
529 ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk"); 534 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true);
530 if (ret)
531 DBG("failed to get (optional) lut_clk clock");
532 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
533 if (ret) 535 if (ret)
534 goto fail; 536 goto fail;
535 537
538 /* optional clocks: */
539 get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false);
540
536 /* we need to set a default rate before enabling. Set a safe 541 /* we need to set a default rate before enabling. Set a safe
537 * rate first, then figure out hw revision, and then set a 542 * rate first, then figure out hw revision, and then set a
538 * more optimal rate: 543 * more optimal rate:
@@ -549,15 +554,23 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
549 } 554 }
550 555
551 config = mdp5_cfg_get_config(mdp5_kms->cfg); 556 config = mdp5_cfg_get_config(mdp5_kms->cfg);
557 mdp5_kms->caps = config->hw->mdp.caps;
552 558
553 /* TODO: compute core clock rate at runtime */ 559 /* TODO: compute core clock rate at runtime */
554 clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); 560 clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
555 561
556 mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); 562 /*
557 if (IS_ERR(mdp5_kms->smp)) { 563 * Some chipsets have a Shared Memory Pool (SMP), while others
558 ret = PTR_ERR(mdp5_kms->smp); 564 * have dedicated latency buffering per source pipe instead;
559 mdp5_kms->smp = NULL; 565 * this section initializes the SMP:
560 goto fail; 566 */
567 if (mdp5_kms->caps & MDP_CAP_SMP) {
568 mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
569 if (IS_ERR(mdp5_kms->smp)) {
570 ret = PTR_ERR(mdp5_kms->smp);
571 mdp5_kms->smp = NULL;
572 goto fail;
573 }
561 } 574 }
562 575
563 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 576 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
@@ -586,6 +599,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
586 if (IS_ERR(mmu)) { 599 if (IS_ERR(mmu)) {
587 ret = PTR_ERR(mmu); 600 ret = PTR_ERR(mmu);
588 dev_err(dev->dev, "failed to init iommu: %d\n", ret); 601 dev_err(dev->dev, "failed to init iommu: %d\n", ret);
602 iommu_domain_free(config->platform.iommu);
589 goto fail; 603 goto fail;
590 } 604 }
591 605
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index 0bb62423586e..84f65d415598 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -32,6 +32,8 @@ struct mdp5_kms {
32 struct drm_device *dev; 32 struct drm_device *dev;
33 33
34 struct mdp5_cfg_handler *cfg; 34 struct mdp5_cfg_handler *cfg;
35 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */
36
35 37
36 /* mapper-id used to request GEM buffer mapped for scanout: */ 38 /* mapper-id used to request GEM buffer mapped for scanout: */
37 int id; 39 int id;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index a0f5ff0ce8dc..81cd49045ffc 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -500,7 +500,7 @@ static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
500 500
501static int calc_scalex_steps(struct drm_plane *plane, 501static int calc_scalex_steps(struct drm_plane *plane,
502 uint32_t pixel_format, uint32_t src, uint32_t dest, 502 uint32_t pixel_format, uint32_t src, uint32_t dest,
503 uint32_t phasex_steps[2]) 503 uint32_t phasex_steps[COMP_MAX])
504{ 504{
505 struct mdp5_kms *mdp5_kms = get_kms(plane); 505 struct mdp5_kms *mdp5_kms = get_kms(plane);
506 struct device *dev = mdp5_kms->dev->dev; 506 struct device *dev = mdp5_kms->dev->dev;
@@ -516,15 +516,16 @@ static int calc_scalex_steps(struct drm_plane *plane,
516 516
517 hsub = drm_format_horz_chroma_subsampling(pixel_format); 517 hsub = drm_format_horz_chroma_subsampling(pixel_format);
518 518
519 phasex_steps[0] = phasex_step; 519 phasex_steps[COMP_0] = phasex_step;
520 phasex_steps[1] = phasex_step / hsub; 520 phasex_steps[COMP_3] = phasex_step;
521 phasex_steps[COMP_1_2] = phasex_step / hsub;
521 522
522 return 0; 523 return 0;
523} 524}
524 525
525static int calc_scaley_steps(struct drm_plane *plane, 526static int calc_scaley_steps(struct drm_plane *plane,
526 uint32_t pixel_format, uint32_t src, uint32_t dest, 527 uint32_t pixel_format, uint32_t src, uint32_t dest,
527 uint32_t phasey_steps[2]) 528 uint32_t phasey_steps[COMP_MAX])
528{ 529{
529 struct mdp5_kms *mdp5_kms = get_kms(plane); 530 struct mdp5_kms *mdp5_kms = get_kms(plane);
530 struct device *dev = mdp5_kms->dev->dev; 531 struct device *dev = mdp5_kms->dev->dev;
@@ -540,46 +541,127 @@ static int calc_scaley_steps(struct drm_plane *plane,
540 541
541 vsub = drm_format_vert_chroma_subsampling(pixel_format); 542 vsub = drm_format_vert_chroma_subsampling(pixel_format);
542 543
543 phasey_steps[0] = phasey_step; 544 phasey_steps[COMP_0] = phasey_step;
544 phasey_steps[1] = phasey_step / vsub; 545 phasey_steps[COMP_3] = phasey_step;
546 phasey_steps[COMP_1_2] = phasey_step / vsub;
545 547
546 return 0; 548 return 0;
547} 549}
548 550
549static uint32_t get_scale_config(enum mdp_chroma_samp_type chroma_sample, 551static uint32_t get_scale_config(const struct mdp_format *format,
550 uint32_t src, uint32_t dest, bool hor) 552 uint32_t src, uint32_t dst, bool horz)
551{ 553{
552 uint32_t y_filter = (src <= dest) ? SCALE_FILTER_CA : SCALE_FILTER_PCMN; 554 bool scaling = format->is_yuv ? true : (src != dst);
553 uint32_t y_a_filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 555 uint32_t sub, pix_fmt = format->base.pixel_format;
554 uint32_t uv_filter = ((src / 2) <= dest) ? /* 2x upsample */ 556 uint32_t ya_filter, uv_filter;
555 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 557 bool yuv = format->is_yuv;
556 uint32_t value = 0; 558
557 559 if (!scaling)
558 if (chroma_sample == CHROMA_420 || chroma_sample == CHROMA_H2V1) { 560 return 0;
559 if (hor) 561
560 value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 562 if (yuv) {
561 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_filter) | 563 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
562 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter) | 564 drm_format_vert_chroma_subsampling(pix_fmt);
563 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter); 565 uv_filter = ((src / sub) <= dst) ?
564 else 566 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
565 value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
566 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_filter) |
567 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter) |
568 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter);
569 } else if (src != dest) {
570 if (hor)
571 value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
572 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_a_filter) |
573 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter);
574 else
575 value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
576 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_a_filter) |
577 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter);
578 } 567 }
568 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
579 569
580 return value; 570 if (horz)
571 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
572 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
573 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
574 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
575 else
576 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
577 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
578 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
579 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
581} 580}
582 581
582static void calc_pixel_ext(const struct mdp_format *format,
583 uint32_t src, uint32_t dst, uint32_t phase_step[2],
584 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
585 bool horz)
586{
587 bool scaling = format->is_yuv ? true : (src != dst);
588 int i;
589
590 /*
591 * Note:
592 * We assume here that:
593 * 1. PCMN filter is used for downscale
594 * 2. bilinear filter is used for upscale
595 * 3. we are in a single pipe configuration
596 */
597
598 for (i = 0; i < COMP_MAX; i++) {
599 pix_ext_edge1[i] = 0;
600 pix_ext_edge2[i] = scaling ? 1 : 0;
601 }
602}
603
604static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
605 const struct mdp_format *format,
606 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
607 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
608{
609 uint32_t pix_fmt = format->base.pixel_format;
610 uint32_t lr, tb, req;
611 int i;
612
613 for (i = 0; i < COMP_MAX; i++) {
614 uint32_t roi_w = src_w;
615 uint32_t roi_h = src_h;
616
617 if (format->is_yuv && i == COMP_1_2) {
618 roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
619 roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
620 }
621
622 lr = (pe_left[i] >= 0) ?
623 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
624 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
625
626 lr |= (pe_right[i] >= 0) ?
627 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
628 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
629
630 tb = (pe_top[i] >= 0) ?
631 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
632 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
633
634 tb |= (pe_bottom[i] >= 0) ?
635 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
636 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
637
638 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
639 pe_left[i] + pe_right[i]);
640
641 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
642 pe_top[i] + pe_bottom[i]);
643
644 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
645 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
646 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
647
648 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
649 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
650 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
651 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
652 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
653 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
654
655 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
656 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
657 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
658 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
659 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
660 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
661 }
662}
663
664
583static int mdp5_plane_mode_set(struct drm_plane *plane, 665static int mdp5_plane_mode_set(struct drm_plane *plane,
584 struct drm_crtc *crtc, struct drm_framebuffer *fb, 666 struct drm_crtc *crtc, struct drm_framebuffer *fb,
585 int crtc_x, int crtc_y, 667 int crtc_x, int crtc_y,
@@ -593,8 +675,10 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
593 enum mdp5_pipe pipe = mdp5_plane->pipe; 675 enum mdp5_pipe pipe = mdp5_plane->pipe;
594 const struct mdp_format *format; 676 const struct mdp_format *format;
595 uint32_t nplanes, config = 0; 677 uint32_t nplanes, config = 0;
596 /* below array -> index 0: comp 0/3 ; index 1: comp 1/2 */ 678 uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,};
597 uint32_t phasex_step[2] = {0,}, phasey_step[2] = {0,}; 679 bool pe = mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT;
680 int pe_left[COMP_MAX], pe_right[COMP_MAX];
681 int pe_top[COMP_MAX], pe_bottom[COMP_MAX];
598 uint32_t hdecm = 0, vdecm = 0; 682 uint32_t hdecm = 0, vdecm = 0;
599 uint32_t pix_format; 683 uint32_t pix_format;
600 bool vflip, hflip; 684 bool vflip, hflip;
@@ -621,10 +705,12 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
621 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 705 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
622 706
623 /* Request some memory from the SMP: */ 707 /* Request some memory from the SMP: */
624 ret = mdp5_smp_request(mdp5_kms->smp, 708 if (mdp5_kms->smp) {
625 mdp5_plane->pipe, format, src_w, false); 709 ret = mdp5_smp_request(mdp5_kms->smp,
626 if (ret) 710 mdp5_plane->pipe, format, src_w, false);
627 return ret; 711 if (ret)
712 return ret;
713 }
628 714
629 /* 715 /*
630 * Currently we update the hw for allocations/requests immediately, 716 * Currently we update the hw for allocations/requests immediately,
@@ -632,7 +718,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
632 * would move into atomic->check_plane_state(), while updating the 718 * would move into atomic->check_plane_state(), while updating the
633 * hw would remain here: 719 * hw would remain here:
634 */ 720 */
635 mdp5_smp_configure(mdp5_kms->smp, pipe); 721 if (mdp5_kms->smp)
722 mdp5_smp_configure(mdp5_kms->smp, pipe);
636 723
637 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step); 724 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step);
638 if (ret) 725 if (ret)
@@ -642,11 +729,18 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
642 if (ret) 729 if (ret)
643 return ret; 730 return ret;
644 731
732 if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
733 calc_pixel_ext(format, src_w, crtc_w, phasex_step,
734 pe_left, pe_right, true);
735 calc_pixel_ext(format, src_h, crtc_h, phasey_step,
736 pe_top, pe_bottom, false);
737 }
738
645 /* TODO calc hdecm, vdecm */ 739 /* TODO calc hdecm, vdecm */
646 740
647 /* SCALE is used to both scale and up-sample chroma components */ 741 /* SCALE is used to both scale and up-sample chroma components */
648 config |= get_scale_config(format->chroma_sample, src_w, crtc_w, true); 742 config |= get_scale_config(format, src_w, crtc_w, true);
649 config |= get_scale_config(format->chroma_sample, src_h, crtc_h, false); 743 config |= get_scale_config(format, src_h, crtc_h, false);
650 DBG("scale config = %x", config); 744 DBG("scale config = %x", config);
651 745
652 hflip = !!(pstate->rotation & BIT(DRM_REFLECT_X)); 746 hflip = !!(pstate->rotation & BIT(DRM_REFLECT_X));
@@ -695,20 +789,26 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
695 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 789 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
696 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 790 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
697 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 791 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
792 COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
698 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 793 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
699 794
700 /* not using secure mode: */ 795 /* not using secure mode: */
701 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 796 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
702 797
798 if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT)
799 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
800 src_w, pe_left, pe_right,
801 src_h, pe_top, pe_bottom);
802
703 if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) { 803 if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) {
704 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 804 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
705 phasex_step[0]); 805 phasex_step[COMP_0]);
706 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 806 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
707 phasey_step[0]); 807 phasey_step[COMP_0]);
708 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 808 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
709 phasex_step[1]); 809 phasex_step[COMP_1_2]);
710 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 810 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
711 phasey_step[1]); 811 phasey_step[COMP_1_2]);
712 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 812 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
713 MDP5_PIPE_DECIMATION_VERT(vdecm) | 813 MDP5_PIPE_DECIMATION_VERT(vdecm) |
714 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 814 MDP5_PIPE_DECIMATION_HORZ(hdecm));
@@ -738,7 +838,8 @@ void mdp5_plane_complete_flip(struct drm_plane *plane)
738 838
739 DBG("%s: complete flip", mdp5_plane->name); 839 DBG("%s: complete flip", mdp5_plane->name);
740 840
741 mdp5_smp_commit(mdp5_kms->smp, pipe); 841 if (mdp5_kms->smp)
842 mdp5_smp_commit(mdp5_kms->smp, pipe);
742 843
743 to_mdp5_plane_state(plane->state)->pending = false; 844 to_mdp5_plane_state(plane->state)->pending = false;
744} 845}
@@ -764,7 +865,7 @@ void mdp5_plane_complete_commit(struct drm_plane *plane,
764 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); 865 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
765 enum mdp5_pipe pipe = mdp5_plane->pipe; 866 enum mdp5_pipe pipe = mdp5_plane->pipe;
766 867
767 if (!plane_enabled(plane->state)) { 868 if (!plane_enabled(plane->state) && mdp5_kms->smp) {
768 DBG("%s: free SMP", mdp5_plane->name); 869 DBG("%s: free SMP", mdp5_plane->name);
769 mdp5_smp_release(mdp5_kms->smp, pipe); 870 mdp5_smp_release(mdp5_kms->smp, pipe);
770 } 871 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
index 563cca972dcb..6f425c25d9fe 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -90,7 +90,7 @@
90struct mdp5_smp { 90struct mdp5_smp {
91 struct drm_device *dev; 91 struct drm_device *dev;
92 92
93 const struct mdp5_smp_block *cfg; 93 uint8_t reserved[MAX_CLIENTS]; /* fixed MMBs allocation per client */
94 94
95 int blk_cnt; 95 int blk_cnt;
96 int blk_size; 96 int blk_size;
@@ -141,10 +141,10 @@ static int smp_request_block(struct mdp5_smp *smp,
141 struct mdp5_kms *mdp5_kms = get_kms(smp); 141 struct mdp5_kms *mdp5_kms = get_kms(smp);
142 struct mdp5_client_smp_state *ps = &smp->client_state[cid]; 142 struct mdp5_client_smp_state *ps = &smp->client_state[cid];
143 int i, ret, avail, cur_nblks, cnt = smp->blk_cnt; 143 int i, ret, avail, cur_nblks, cnt = smp->blk_cnt;
144 int reserved; 144 uint8_t reserved;
145 unsigned long flags; 145 unsigned long flags;
146 146
147 reserved = smp->cfg->reserved[cid]; 147 reserved = smp->reserved[cid];
148 148
149 spin_lock_irqsave(&smp->state_lock, flags); 149 spin_lock_irqsave(&smp->state_lock, flags);
150 150
@@ -405,12 +405,12 @@ struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, const struct mdp5_smp_blo
405 } 405 }
406 406
407 smp->dev = dev; 407 smp->dev = dev;
408 smp->cfg = cfg;
409 smp->blk_cnt = cfg->mmb_count; 408 smp->blk_cnt = cfg->mmb_count;
410 smp->blk_size = cfg->mmb_size; 409 smp->blk_size = cfg->mmb_size;
411 410
412 /* statically tied MMBs cannot be re-allocated: */ 411 /* statically tied MMBs cannot be re-allocated: */
413 bitmap_copy(smp->state, cfg->reserved_state, smp->blk_cnt); 412 bitmap_copy(smp->state, cfg->reserved_state, smp->blk_cnt);
413 memcpy(smp->reserved, cfg->reserved, sizeof(smp->reserved));
414 spin_lock_init(&smp->state_lock); 414 spin_lock_init(&smp->state_lock);
415 415
416 return smp; 416 return smp;
diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
index 4f792c4e40f4..0aec1ac1f6d0 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
@@ -78,6 +78,13 @@ enum mdp_alpha_type {
78 BG_PIXEL = 3, 78 BG_PIXEL = 3,
79}; 79};
80 80
81enum mdp_component_type {
82 COMP_0 = 0,
83 COMP_1_2 = 1,
84 COMP_3 = 2,
85 COMP_MAX = 3,
86};
87
81enum mdp_bpc { 88enum mdp_bpc {
82 BPC1 = 0, 89 BPC1 = 0,
83 BPC5 = 1, 90 BPC5 = 1,
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h b/drivers/gpu/drm/msm/mdp/mdp_kms.h
index 46a94e7d50e2..303130320748 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h
@@ -100,12 +100,18 @@ struct mdp_format {
100uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only); 100uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
101const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format); 101const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
102 102
103/* MDP capabilities */
104#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
105#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */
106#define MDP_CAP_CDM BIT(2) /* Chroma Down Module (HDMI 2.0 YUV) */
107
103/* MDP pipe capabilities */ 108/* MDP pipe capabilities */
104#define MDP_PIPE_CAP_HFLIP BIT(0) 109#define MDP_PIPE_CAP_HFLIP BIT(0)
105#define MDP_PIPE_CAP_VFLIP BIT(1) 110#define MDP_PIPE_CAP_VFLIP BIT(1)
106#define MDP_PIPE_CAP_SCALE BIT(2) 111#define MDP_PIPE_CAP_SCALE BIT(2)
107#define MDP_PIPE_CAP_CSC BIT(3) 112#define MDP_PIPE_CAP_CSC BIT(3)
108#define MDP_PIPE_CAP_DECIMATION BIT(4) 113#define MDP_PIPE_CAP_DECIMATION BIT(4)
114#define MDP_PIPE_CAP_SW_PIX_EXT BIT(5)
109 115
110static inline bool pipe_supports_yuv(uint32_t pipe_caps) 116static inline bool pipe_supports_yuv(uint32_t pipe_caps)
111{ 117{
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index d170131b0978..b88ce514eb8e 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -21,11 +21,9 @@
21 21
22static void msm_fb_output_poll_changed(struct drm_device *dev) 22static void msm_fb_output_poll_changed(struct drm_device *dev)
23{ 23{
24#ifdef CONFIG_DRM_MSM_FBDEV
25 struct msm_drm_private *priv = dev->dev_private; 24 struct msm_drm_private *priv = dev->dev_private;
26 if (priv->fbdev) 25 if (priv->fbdev)
27 drm_fb_helper_hotplug_event(priv->fbdev); 26 drm_fb_helper_hotplug_event(priv->fbdev);
28#endif
29} 27}
30 28
31static const struct drm_mode_config_funcs mode_config_funcs = { 29static const struct drm_mode_config_funcs mode_config_funcs = {
@@ -56,7 +54,7 @@ module_param(reglog, bool, 0600);
56#define reglog 0 54#define reglog 0
57#endif 55#endif
58 56
59#ifdef CONFIG_DRM_MSM_FBDEV 57#ifdef CONFIG_DRM_FBDEV_EMULATION
60static bool fbdev = true; 58static bool fbdev = true;
61MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 59MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
62module_param(fbdev, bool, 0600); 60module_param(fbdev, bool, 0600);
@@ -423,7 +421,7 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
423 421
424 drm_mode_config_reset(dev); 422 drm_mode_config_reset(dev);
425 423
426#ifdef CONFIG_DRM_MSM_FBDEV 424#ifdef CONFIG_DRM_FBDEV_EMULATION
427 if (fbdev) 425 if (fbdev)
428 priv->fbdev = msm_fbdev_init(dev); 426 priv->fbdev = msm_fbdev_init(dev);
429#endif 427#endif
@@ -491,11 +489,9 @@ static void msm_preclose(struct drm_device *dev, struct drm_file *file)
491 489
492static void msm_lastclose(struct drm_device *dev) 490static void msm_lastclose(struct drm_device *dev)
493{ 491{
494#ifdef CONFIG_DRM_MSM_FBDEV
495 struct msm_drm_private *priv = dev->dev_private; 492 struct msm_drm_private *priv = dev->dev_private;
496 if (priv->fbdev) 493 if (priv->fbdev)
497 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); 494 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
498#endif
499} 495}
500 496
501static irqreturn_t msm_irq(int irq, void *arg) 497static irqreturn_t msm_irq(int irq, void *arg)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 8f70d9248ac5..6b02ada6579a 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -651,6 +651,14 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
651 if (iommu) { 651 if (iommu) {
652 dev_info(drm->dev, "%s: using IOMMU\n", name); 652 dev_info(drm->dev, "%s: using IOMMU\n", name);
653 gpu->mmu = msm_iommu_new(&pdev->dev, iommu); 653 gpu->mmu = msm_iommu_new(&pdev->dev, iommu);
654 if (IS_ERR(gpu->mmu)) {
655 ret = PTR_ERR(gpu->mmu);
656 dev_err(drm->dev, "failed to init iommu: %d\n", ret);
657 gpu->mmu = NULL;
658 iommu_domain_free(iommu);
659 goto fail;
660 }
661
654 } else { 662 } else {
655 dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); 663 dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
656 } 664 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 06:06:30 -0400