diff options
author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2017-09-29 07:49:47 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2017-12-19 03:32:00 -0500 |
commit | d312fe2ef581b3cd0971ffa4ed24677b9ea9b4bc (patch) | |
tree | 800321dbae1b79291c7cecd3d7ebc3c9f8026247 /drivers | |
parent | b3d5a8d77eb807aba7cdbb71f15d0161b53b399b (diff) |
drm/omap: DMM: In case of error/timeout in wait_status() print the reason
If the wait_status() fails either because of an error reported in the
STATUS register or because of a timeout waiting for the wait_mask, print
information which might help diagnose the reason.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c index c60a85e82c6d..e3725dc60e2c 100644 --- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c +++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | |||
@@ -121,14 +121,22 @@ static int wait_status(struct refill_engine *engine, uint32_t wait_mask) | |||
121 | while (true) { | 121 | while (true) { |
122 | r = dmm_read(dmm, reg[PAT_STATUS][engine->id]); | 122 | r = dmm_read(dmm, reg[PAT_STATUS][engine->id]); |
123 | err = r & DMM_PATSTATUS_ERR; | 123 | err = r & DMM_PATSTATUS_ERR; |
124 | if (err) | 124 | if (err) { |
125 | dev_err(dmm->dev, | ||
126 | "%s: error (engine%d). PAT_STATUS: 0x%08x\n", | ||
127 | __func__, engine->id, r); | ||
125 | return -EFAULT; | 128 | return -EFAULT; |
129 | } | ||
126 | 130 | ||
127 | if ((r & wait_mask) == wait_mask) | 131 | if ((r & wait_mask) == wait_mask) |
128 | break; | 132 | break; |
129 | 133 | ||
130 | if (--i == 0) | 134 | if (--i == 0) { |
135 | dev_err(dmm->dev, | ||
136 | "%s: timeout (engine%d). PAT_STATUS: 0x%08x\n", | ||
137 | __func__, engine->id, r); | ||
131 | return -ETIMEDOUT; | 138 | return -ETIMEDOUT; |
139 | } | ||
132 | 140 | ||
133 | udelay(1); | 141 | udelay(1); |
134 | } | 142 | } |