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authorAlexandre Courbot <acourbot@nvidia.com>2017-03-29 05:31:18 -0400
committerBen Skeggs <bskeggs@redhat.com>2017-04-06 00:39:04 -0400
commitb9a995def69671b4f5f7a06a4bb5c89ad31ada1c (patch)
tree31bc6d6eee6beea7f7d762d4c4cf890694f9dc18 /drivers
parentfdde00ed1193cd3b179a2c93f9508e1d090c2062 (diff)
drm/nouveau/mc: add GP10B support
GP10B's MC is compatible with GP100's, but engines need to be explicitly put out of ELPG during init. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c17
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c49
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h6
5 files changed, 69 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
index e68ba636741b..58f10890c3b6 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
@@ -29,4 +29,5 @@ int gf100_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
29int gk104_mc_new(struct nvkm_device *, int, struct nvkm_mc **); 29int gk104_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
30int gk20a_mc_new(struct nvkm_device *, int, struct nvkm_mc **); 30int gk20a_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
31int gp100_mc_new(struct nvkm_device *, int, struct nvkm_mc **); 31int gp100_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
32int gp10b_mc_new(struct nvkm_device *, int, struct nvkm_mc **);
32#endif 33#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
index 12943f92c206..2befbe36dc28 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
@@ -11,3 +11,4 @@ nvkm-y += nvkm/subdev/mc/gf100.o
11nvkm-y += nvkm/subdev/mc/gk104.o 11nvkm-y += nvkm/subdev/mc/gk104.o
12nvkm-y += nvkm/subdev/mc/gk20a.o 12nvkm-y += nvkm/subdev/mc/gk20a.o
13nvkm-y += nvkm/subdev/mc/gp100.o 13nvkm-y += nvkm/subdev/mc/gp100.o
14nvkm-y += nvkm/subdev/mc/gp10b.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c
index 4d22f4abd6de..7321ad3758c3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c
@@ -42,7 +42,7 @@ gp100_mc_intr_update(struct gp100_mc *mc)
42 } 42 }
43} 43}
44 44
45static void 45void
46gp100_mc_intr_unarm(struct nvkm_mc *base) 46gp100_mc_intr_unarm(struct nvkm_mc *base)
47{ 47{
48 struct gp100_mc *mc = gp100_mc(base); 48 struct gp100_mc *mc = gp100_mc(base);
@@ -53,7 +53,7 @@ gp100_mc_intr_unarm(struct nvkm_mc *base)
53 spin_unlock_irqrestore(&mc->lock, flags); 53 spin_unlock_irqrestore(&mc->lock, flags);
54} 54}
55 55
56static void 56void
57gp100_mc_intr_rearm(struct nvkm_mc *base) 57gp100_mc_intr_rearm(struct nvkm_mc *base)
58{ 58{
59 struct gp100_mc *mc = gp100_mc(base); 59 struct gp100_mc *mc = gp100_mc(base);
@@ -64,7 +64,7 @@ gp100_mc_intr_rearm(struct nvkm_mc *base)
64 spin_unlock_irqrestore(&mc->lock, flags); 64 spin_unlock_irqrestore(&mc->lock, flags);
65} 65}
66 66
67static void 67void
68gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) 68gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr)
69{ 69{
70 struct gp100_mc *mc = gp100_mc(base); 70 struct gp100_mc *mc = gp100_mc(base);
@@ -87,13 +87,14 @@ gp100_mc = {
87}; 87};
88 88
89int 89int
90gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) 90gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device,
91 int index, struct nvkm_mc **pmc)
91{ 92{
92 struct gp100_mc *mc; 93 struct gp100_mc *mc;
93 94
94 if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL))) 95 if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL)))
95 return -ENOMEM; 96 return -ENOMEM;
96 nvkm_mc_ctor(&gp100_mc, device, index, &mc->base); 97 nvkm_mc_ctor(func, device, index, &mc->base);
97 *pmc = &mc->base; 98 *pmc = &mc->base;
98 99
99 spin_lock_init(&mc->lock); 100 spin_lock_init(&mc->lock);
@@ -101,3 +102,9 @@ gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
101 mc->mask = 0x7fffffff; 102 mc->mask = 0x7fffffff;
102 return 0; 103 return 0;
103} 104}
105
106int
107gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
108{
109 return gp100_mc_new_(&gp100_mc, device, index, pmc);
110}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c
new file mode 100644
index 000000000000..2283e3b74277
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "priv.h"
25
26void
27gp10b_mc_init(struct nvkm_mc *mc)
28{
29 struct nvkm_device *device = mc->subdev.device;
30 nvkm_wr32(device, 0x000200, 0xffffffff); /* everything on */
31 nvkm_wr32(device, 0x00020c, 0xffffffff); /* everything out of ELPG */
32}
33
34static const struct nvkm_mc_func
35gp10b_mc = {
36 .init = gp10b_mc_init,
37 .intr = gk104_mc_intr,
38 .intr_unarm = gp100_mc_intr_unarm,
39 .intr_rearm = gp100_mc_intr_rearm,
40 .intr_mask = gp100_mc_intr_mask,
41 .intr_stat = gf100_mc_intr_stat,
42 .reset = gk104_mc_reset,
43};
44
45int
46gp10b_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
47{
48 return gp100_mc_new_(&gp10b_mc, device, index, pmc);
49}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
index 4f0576a06d24..3be4126441e4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
@@ -41,12 +41,18 @@ extern const struct nvkm_mc_map nv17_mc_reset[];
41void nv44_mc_init(struct nvkm_mc *); 41void nv44_mc_init(struct nvkm_mc *);
42 42
43void nv50_mc_init(struct nvkm_mc *); 43void nv50_mc_init(struct nvkm_mc *);
44void gk104_mc_init(struct nvkm_mc *);
44 45
45void gf100_mc_intr_unarm(struct nvkm_mc *); 46void gf100_mc_intr_unarm(struct nvkm_mc *);
46void gf100_mc_intr_rearm(struct nvkm_mc *); 47void gf100_mc_intr_rearm(struct nvkm_mc *);
47void gf100_mc_intr_mask(struct nvkm_mc *, u32, u32); 48void gf100_mc_intr_mask(struct nvkm_mc *, u32, u32);
48u32 gf100_mc_intr_stat(struct nvkm_mc *); 49u32 gf100_mc_intr_stat(struct nvkm_mc *);
49void gf100_mc_unk260(struct nvkm_mc *, u32); 50void gf100_mc_unk260(struct nvkm_mc *, u32);
51void gp100_mc_intr_unarm(struct nvkm_mc *);
52void gp100_mc_intr_rearm(struct nvkm_mc *);
53void gp100_mc_intr_mask(struct nvkm_mc *, u32, u32);
54int gp100_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, int,
55 struct nvkm_mc **);
50 56
51extern const struct nvkm_mc_map gk104_mc_intr[]; 57extern const struct nvkm_mc_map gk104_mc_intr[];
52extern const struct nvkm_mc_map gk104_mc_reset[]; 58extern const struct nvkm_mc_map gk104_mc_reset[];