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authorZhenyu Wang <zhenyuw@linux.intel.com>2018-02-22 02:16:18 -0500
committerZhenyu Wang <zhenyuw@linux.intel.com>2018-03-06 00:19:26 -0500
commitb52646fd5bb40422be4ba8e1c3f46c23de6965a3 (patch)
treead05b71eb8eebe33b550d070cabf64ca4eb596e3 /drivers
parent253fe56ea96546bda371d2397443dfe9ee978557 (diff)
drm/i915/gvt: Fix check error on hws_pga_write() fail message
Fix below check error by using proper failure message output. drivers/gpu/drm/i915//gvt/handlers.c:1392 hws_pga_write() error: 'vgpu' dereferencing possible ERR_PTR() drivers/gpu/drm/i915//gvt/handlers.c:1402 hws_pga_write() error: 'vgpu' dereferencing possible ERR_PTR() Reviewed-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7792711e01e3..112f2ec7c25f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1391,8 +1391,8 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1391 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1391 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1392 1392
1393 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1393 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1394 gvt_vgpu_err("VM(%d) write invalid HWSP address, reg:0x%x, value:0x%x\n", 1394 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1395 vgpu->id, offset, value); 1395 offset, value);
1396 return -EINVAL; 1396 return -EINVAL;
1397 } 1397 }
1398 /* 1398 /*
@@ -1401,8 +1401,8 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1401 * support BDW, SKL or other platforms with same HWSP registers. 1401 * support BDW, SKL or other platforms with same HWSP registers.
1402 */ 1402 */
1403 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1403 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1404 gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n", 1404 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1405 vgpu->id, offset); 1405 offset);
1406 return -EINVAL; 1406 return -EINVAL;
1407 } 1407 }
1408 vgpu->hws_pga[ring_id] = value; 1408 vgpu->hws_pga[ring_id] = value;