clk: imx: Fix fractional clock set rate computation

Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be
 temp64 = rate * 2 - divfi * parent_rate * 8, instead of:
 temp64 = (rate * 2 - divfi) * parent_rate

Fixes: 6209624b9a5c1e ("clk: imx: Add fractional PLL output clock")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
index 0026c3969b1e..76b9eb15604e 100644
--- a/drivers/clk/imx/clk-frac-pll.c
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -155,13 +155,14 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 {
         struct clk_frac_pll *pll = to_clk_frac_pll(hw);
         u32 val, divfi, divff;
-        u64 temp64 = parent_rate;
+        u64 temp64;
         int ret;
 
         parent_rate *= 8;
         rate *= 2;
         divfi = rate / parent_rate;
-        temp64 *= rate - divfi;
+        temp64 = parent_rate * divfi;
+        temp64 = rate - temp64;
         temp64 *= PLL_FRAC_DENOM;
         do_div(temp64, parent_rate);
         divff = temp64;