diff options
| author | Anson Huang <anson.huang@nxp.com> | 2019-04-26 02:53:14 -0400 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-05-03 12:31:54 -0400 |
| commit | a5a627c676590aaf381f38279ffdfacc963f18f4 (patch) | |
| tree | bb7509698434e652eaa78a2ab0190e10b71c853a /drivers | |
| parent | 53dd5c709b335545eec76e3a401ad82764d42b6a (diff) | |
clk: imx: correct pfdv2 gate_bit/vld_bit operations
The operations of pfdv2 gate_bit/valid_bit are incorrect,
they are defined as u8 for bit offset, but gate_bit is
actually assigned as mask which could be 32 bit long and
it causes overflow, and vld_bit is assigned as bit offset
based on incorrect gate_bit value, it causes incorrect
pfd clock gate status in clock tree, this patch fixes the
issue by assigning them as correct bit offset.
Fixes: 9fcb6be3b6c9 ("clk: imx: add pfdv2 support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/imx/clk-pfdv2.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c index 7e9134b205ab..fb567dcc2118 100644 --- a/drivers/clk/imx/clk-pfdv2.c +++ b/drivers/clk/imx/clk-pfdv2.c | |||
| @@ -43,7 +43,7 @@ static int clk_pfdv2_wait(struct clk_pfdv2 *pfd) | |||
| 43 | { | 43 | { |
| 44 | u32 val; | 44 | u32 val; |
| 45 | 45 | ||
| 46 | return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit, | 46 | return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit), |
| 47 | 0, LOCK_TIMEOUT_US); | 47 | 0, LOCK_TIMEOUT_US); |
| 48 | } | 48 | } |
| 49 | 49 | ||
| @@ -55,7 +55,7 @@ static int clk_pfdv2_enable(struct clk_hw *hw) | |||
| 55 | 55 | ||
| 56 | spin_lock_irqsave(&pfd_lock, flags); | 56 | spin_lock_irqsave(&pfd_lock, flags); |
| 57 | val = readl_relaxed(pfd->reg); | 57 | val = readl_relaxed(pfd->reg); |
| 58 | val &= ~pfd->gate_bit; | 58 | val &= ~(1 << pfd->gate_bit); |
| 59 | writel_relaxed(val, pfd->reg); | 59 | writel_relaxed(val, pfd->reg); |
| 60 | spin_unlock_irqrestore(&pfd_lock, flags); | 60 | spin_unlock_irqrestore(&pfd_lock, flags); |
| 61 | 61 | ||
| @@ -70,7 +70,7 @@ static void clk_pfdv2_disable(struct clk_hw *hw) | |||
| 70 | 70 | ||
| 71 | spin_lock_irqsave(&pfd_lock, flags); | 71 | spin_lock_irqsave(&pfd_lock, flags); |
| 72 | val = readl_relaxed(pfd->reg); | 72 | val = readl_relaxed(pfd->reg); |
| 73 | val |= pfd->gate_bit; | 73 | val |= (1 << pfd->gate_bit); |
| 74 | writel_relaxed(val, pfd->reg); | 74 | writel_relaxed(val, pfd->reg); |
| 75 | spin_unlock_irqrestore(&pfd_lock, flags); | 75 | spin_unlock_irqrestore(&pfd_lock, flags); |
| 76 | } | 76 | } |
| @@ -123,7 +123,7 @@ static int clk_pfdv2_is_enabled(struct clk_hw *hw) | |||
| 123 | { | 123 | { |
| 124 | struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); | 124 | struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); |
| 125 | 125 | ||
| 126 | if (readl_relaxed(pfd->reg) & pfd->gate_bit) | 126 | if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit)) |
| 127 | return 0; | 127 | return 0; |
| 128 | 128 | ||
| 129 | return 1; | 129 | return 1; |
| @@ -180,7 +180,7 @@ struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, | |||
| 180 | return ERR_PTR(-ENOMEM); | 180 | return ERR_PTR(-ENOMEM); |
| 181 | 181 | ||
| 182 | pfd->reg = reg; | 182 | pfd->reg = reg; |
| 183 | pfd->gate_bit = 1 << ((idx + 1) * 8 - 1); | 183 | pfd->gate_bit = (idx + 1) * 8 - 1; |
| 184 | pfd->vld_bit = pfd->gate_bit - 1; | 184 | pfd->vld_bit = pfd->gate_bit - 1; |
| 185 | pfd->frac_off = idx * 8; | 185 | pfd->frac_off = idx * 8; |
| 186 | 186 | ||
