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authorAlex Deucher <alexander.deucher@amd.com>2018-09-20 22:17:17 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-09-26 22:09:10 -0400
commita476e925babedddd709b7a4fb5645f8a160b93bf (patch)
tree48579915f445cf078472c6f96ab7b653012696a6 /drivers
parent68e841abf8fb9a9714924802145f27ac2b06db9d (diff)
drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20
For consistency with other asics. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c32
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c22
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h4
3 files changed, 34 insertions, 24 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 7825c6ad1452..260e0e48dcd6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -743,8 +743,8 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
743 743
744 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 744 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
745 745
746 result = vega20_copy_table_to_smc(hwmgr, 746 result = smum_smc_table_manager(hwmgr,
747 (uint8_t *)pp_table, TABLE_PPTABLE); 747 (uint8_t *)pp_table, TABLE_PPTABLE, false);
748 PP_ASSERT_WITH_CODE(!result, 748 PP_ASSERT_WITH_CODE(!result,
749 "[InitSMCTable] Failed to upload PPtable!", 749 "[InitSMCTable] Failed to upload PPtable!",
750 return result); 750 return result);
@@ -1067,7 +1067,7 @@ static int vega20_od8_initialize_default_settings(
1067 vega20_od8_set_feature_id(hwmgr); 1067 vega20_od8_set_feature_id(hwmgr);
1068 1068
1069 /* Set default values */ 1069 /* Set default values */
1070 ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE); 1070 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1071 PP_ASSERT_WITH_CODE(!ret, 1071 PP_ASSERT_WITH_CODE(!ret,
1072 "Failed to export over drive table!", 1072 "Failed to export over drive table!",
1073 return ret); 1073 return ret);
@@ -1195,7 +1195,7 @@ static int vega20_od8_initialize_default_settings(
1195 } 1195 }
1196 } 1196 }
1197 1197
1198 ret = vega20_copy_table_to_smc(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE); 1198 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1199 PP_ASSERT_WITH_CODE(!ret, 1199 PP_ASSERT_WITH_CODE(!ret,
1200 "Failed to import over drive table!", 1200 "Failed to import over drive table!",
1201 return ret); 1201 return ret);
@@ -1214,7 +1214,7 @@ static int vega20_od8_set_settings(
1214 struct vega20_od8_single_setting *od8_settings = 1214 struct vega20_od8_single_setting *od8_settings =
1215 data->od8_settings.od8_settings_array; 1215 data->od8_settings.od8_settings_array;
1216 1216
1217 ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE); 1217 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1218 PP_ASSERT_WITH_CODE(!ret, 1218 PP_ASSERT_WITH_CODE(!ret,
1219 "Failed to export over drive table!", 1219 "Failed to export over drive table!",
1220 return ret); 1220 return ret);
@@ -1271,7 +1271,7 @@ static int vega20_od8_set_settings(
1271 break; 1271 break;
1272 } 1272 }
1273 1273
1274 ret = vega20_copy_table_to_smc(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE); 1274 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1275 PP_ASSERT_WITH_CODE(!ret, 1275 PP_ASSERT_WITH_CODE(!ret,
1276 "Failed to import over drive table!", 1276 "Failed to import over drive table!",
1277 return ret); 1277 return ret);
@@ -1841,7 +1841,7 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1841 int ret = 0; 1841 int ret = 0;
1842 SmuMetrics_t metrics_table; 1842 SmuMetrics_t metrics_table;
1843 1843
1844 ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS); 1844 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1845 PP_ASSERT_WITH_CODE(!ret, 1845 PP_ASSERT_WITH_CODE(!ret,
1846 "Failed to export SMU METRICS table!", 1846 "Failed to export SMU METRICS table!",
1847 return ret); 1847 return ret);
@@ -1893,7 +1893,7 @@ static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1893 int ret = 0; 1893 int ret = 0;
1894 SmuMetrics_t metrics_table; 1894 SmuMetrics_t metrics_table;
1895 1895
1896 ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS); 1896 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1897 PP_ASSERT_WITH_CODE(!ret, 1897 PP_ASSERT_WITH_CODE(!ret,
1898 "Failed to export SMU METRICS table!", 1898 "Failed to export SMU METRICS table!",
1899 return ret); 1899 return ret);
@@ -2612,18 +2612,18 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2612 data->gfxclk_overdrive = false; 2612 data->gfxclk_overdrive = false;
2613 data->memclk_overdrive = false; 2613 data->memclk_overdrive = false;
2614 2614
2615 ret = vega20_copy_table_from_smc(hwmgr, 2615 ret = smum_smc_table_manager(hwmgr,
2616 (uint8_t *)od_table, 2616 (uint8_t *)od_table,
2617 TABLE_OVERDRIVE); 2617 TABLE_OVERDRIVE, true);
2618 PP_ASSERT_WITH_CODE(!ret, 2618 PP_ASSERT_WITH_CODE(!ret,
2619 "Failed to export overdrive table!", 2619 "Failed to export overdrive table!",
2620 return ret); 2620 return ret);
2621 break; 2621 break;
2622 2622
2623 case PP_OD_COMMIT_DPM_TABLE: 2623 case PP_OD_COMMIT_DPM_TABLE:
2624 ret = vega20_copy_table_to_smc(hwmgr, 2624 ret = smum_smc_table_manager(hwmgr,
2625 (uint8_t *)od_table, 2625 (uint8_t *)od_table,
2626 TABLE_OVERDRIVE); 2626 TABLE_OVERDRIVE, false);
2627 PP_ASSERT_WITH_CODE(!ret, 2627 PP_ASSERT_WITH_CODE(!ret,
2628 "Failed to import overdrive table!", 2628 "Failed to import overdrive table!",
2629 return ret); 2629 return ret);
@@ -2847,8 +2847,8 @@ static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2847 2847
2848 if ((data->water_marks_bitmap & WaterMarksExist) && 2848 if ((data->water_marks_bitmap & WaterMarksExist) &&
2849 !(data->water_marks_bitmap & WaterMarksLoaded)) { 2849 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2850 result = vega20_copy_table_to_smc(hwmgr, 2850 result = smum_smc_table_manager(hwmgr,
2851 (uint8_t *)wm_table, TABLE_WATERMARKS); 2851 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2852 PP_ASSERT_WITH_CODE(!result, 2852 PP_ASSERT_WITH_CODE(!result,
2853 "Failed to update WMTABLE!", 2853 "Failed to update WMTABLE!",
2854 return result); 2854 return result);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
index 52438f56fb79..b7ff7d4d6f44 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
@@ -160,8 +160,8 @@ static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)
160 * @param hwmgr the address of the HW manager 160 * @param hwmgr the address of the HW manager
161 * @param table_id the driver's table ID to copy from 161 * @param table_id the driver's table ID to copy from
162 */ 162 */
163int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr, 163static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
164 uint8_t *table, int16_t table_id) 164 uint8_t *table, int16_t table_id)
165{ 165{
166 struct vega20_smumgr *priv = 166 struct vega20_smumgr *priv =
167 (struct vega20_smumgr *)(hwmgr->smu_backend); 167 (struct vega20_smumgr *)(hwmgr->smu_backend);
@@ -200,8 +200,8 @@ int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
200 * @param hwmgr the address of the HW manager 200 * @param hwmgr the address of the HW manager
201 * @param table_id the table to copy from 201 * @param table_id the table to copy from
202 */ 202 */
203int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr, 203static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
204 uint8_t *table, int16_t table_id) 204 uint8_t *table, int16_t table_id)
205{ 205{
206 struct vega20_smumgr *priv = 206 struct vega20_smumgr *priv =
207 (struct vega20_smumgr *)(hwmgr->smu_backend); 207 (struct vega20_smumgr *)(hwmgr->smu_backend);
@@ -560,6 +560,19 @@ static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
560 return false; 560 return false;
561} 561}
562 562
563static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
564 uint16_t table_id, bool rw)
565{
566 int ret;
567
568 if (rw)
569 ret = vega20_copy_table_from_smc(hwmgr, table, table_id);
570 else
571 ret = vega20_copy_table_to_smc(hwmgr, table, table_id);
572
573 return ret;
574}
575
563const struct pp_smumgr_func vega20_smu_funcs = { 576const struct pp_smumgr_func vega20_smu_funcs = {
564 .smu_init = &vega20_smu_init, 577 .smu_init = &vega20_smu_init,
565 .smu_fini = &vega20_smu_fini, 578 .smu_fini = &vega20_smu_fini,
@@ -571,4 +584,5 @@ const struct pp_smumgr_func vega20_smu_funcs = {
571 .upload_pptable_settings = NULL, 584 .upload_pptable_settings = NULL,
572 .is_dpm_running = vega20_is_dpm_running, 585 .is_dpm_running = vega20_is_dpm_running,
573 .get_argument = vega20_get_argument, 586 .get_argument = vega20_get_argument,
587 .smc_table_manager = vega20_smc_table_manager,
574}; 588};
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
index fd1760146de1..77349c3f0162 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
@@ -47,10 +47,6 @@ struct vega20_smumgr {
47#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 47#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
48#define SMU_FEATURES_HIGH_SHIFT 32 48#define SMU_FEATURES_HIGH_SHIFT 32
49 49
50int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
51 uint8_t *table, int16_t table_id);
52int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
53 uint8_t *table, int16_t table_id);
54int vega20_enable_smc_features(struct pp_hwmgr *hwmgr, 50int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
55 bool enable, uint64_t feature_mask); 51 bool enable, uint64_t feature_mask);
56int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr, 52int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,