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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2017-09-18 04:16:26 -0400
committerVinod Koul <vinod.koul@intel.com>2017-09-21 13:21:07 -0400
commit87a2f622cc6446c7d09ac655b7b9b04886f16a4c (patch)
treede4fa5bff5fac78e3de3465f70ae0e8584f18262 /drivers
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff)
dmaengine: edma: Align the memcpy acnt array size with the transfer
Memory to Memory transfers does not have any special alignment needs regarding to acnt array size, but if one of the areas are in memory mapped regions (like PCIe memory), we need to make sure that the acnt array size is aligned with the mem copy parameters. Before "dmaengine: edma: Optimize memcpy operation" change the memcpy was set up in a different way: acnt == number of bytes in a word based on __ffs((src | dest | len), bcnt and ccnt for looping the necessary number of words to comlete the trasnfer. Instead of reverting the commit we can fix it to make sure that the ACNT size is aligned to the traswnfer. Fixes: df6694f80365a (dmaengine: edma: Optimize memcpy operation) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: stable@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/dma/edma.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 3879f80a4815..a7ea20e7b8e9 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -1143,11 +1143,24 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1143 struct edma_desc *edesc; 1143 struct edma_desc *edesc;
1144 struct device *dev = chan->device->dev; 1144 struct device *dev = chan->device->dev;
1145 struct edma_chan *echan = to_edma_chan(chan); 1145 struct edma_chan *echan = to_edma_chan(chan);
1146 unsigned int width, pset_len; 1146 unsigned int width, pset_len, array_size;
1147 1147
1148 if (unlikely(!echan || !len)) 1148 if (unlikely(!echan || !len))
1149 return NULL; 1149 return NULL;
1150 1150
1151 /* Align the array size (acnt block) with the transfer properties */
1152 switch (__ffs((src | dest | len))) {
1153 case 0:
1154 array_size = SZ_32K - 1;
1155 break;
1156 case 1:
1157 array_size = SZ_32K - 2;
1158 break;
1159 default:
1160 array_size = SZ_32K - 4;
1161 break;
1162 }
1163
1151 if (len < SZ_64K) { 1164 if (len < SZ_64K) {
1152 /* 1165 /*
1153 * Transfer size less than 64K can be handled with one paRAM 1166 * Transfer size less than 64K can be handled with one paRAM
@@ -1169,7 +1182,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1169 * When the full_length is multibple of 32767 one slot can be 1182 * When the full_length is multibple of 32767 one slot can be
1170 * used to complete the transfer. 1183 * used to complete the transfer.
1171 */ 1184 */
1172 width = SZ_32K - 1; 1185 width = array_size;
1173 pset_len = rounddown(len, width); 1186 pset_len = rounddown(len, width);
1174 /* One slot is enough for lengths multiple of (SZ_32K -1) */ 1187 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1175 if (unlikely(pset_len == len)) 1188 if (unlikely(pset_len == len))
@@ -1217,7 +1230,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1217 } 1230 }
1218 dest += pset_len; 1231 dest += pset_len;
1219 src += pset_len; 1232 src += pset_len;
1220 pset_len = width = len % (SZ_32K - 1); 1233 pset_len = width = len % array_size;
1221 1234
1222 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, 1235 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1223 width, pset_len, DMA_MEM_TO_MEM); 1236 width, pset_len, DMA_MEM_TO_MEM);