diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-04-22 20:14:29 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-04-22 20:14:29 -0400 |
commit | 867ab4b2fcc3f840e9cc378a812e07f850795e6f (patch) | |
tree | bd5c334f31dad4cfffe7d67c8053693ca5b7e48d /drivers | |
parent | 5ec83b22a2dd13180762c89698e4e2c2881a423c (diff) | |
parent | 221bda4b5f1abfd74159d7bf3703affa62468030 (diff) |
Merge tag 'drm-fixes-for-v4.17-rc2' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Exynos, i915, vc4, amdgpu fixes.
i915:
- an oops fix
- two race fixes
- some gvt fixes
amdgpu:
- dark screen fix
- clk/voltage fix
- vega12 smu fix
vc4:
- memory leak fix
exynos just drops some code"
* tag 'drm-fixes-for-v4.17-rc2' of git://people.freedesktop.org/~airlied/linux: (23 commits)
drm/amd/powerplay: header file interface to SMU update
drm/amd/pp: Fix bug voltage can't be OD separately on VI
drm/amd/display: Don't program bypass on linear regamma LUT
drm/i915: Fix LSPCON TMDS output buffer enabling from low-power state
drm/i915/audio: Fix audio detection issue on GLK
drm/i915: Call i915_perf_fini() on init_hw error unwind
drm/i915/bios: filter out invalid DDC pins from VBT child devices
drm/i915/pmu: Inspect runtime PM state more carefully while estimating RC6
drm/i915: Do no use kfree() to free a kmem_cache_alloc() return value
drm/exynos: exynos_drm_fb -> drm_framebuffer
drm/exynos: Move dma_addr out of exynos_drm_fb
drm/exynos: Move GEM BOs to drm_framebuffer
drm: Fix HDCP downstream dev count read
drm/vc4: Fix memory leak during BO teardown
drm/i915/execlists: Clear user-active flag on preemption completion
drm/i915/gvt: Add drm_format_mod update
drm/i915/gvt: Disable primary/sprite/cursor plane at virtual display initialization
drm/i915/gvt: Delete redundant error message in fb_decode.c
drm/i915/gvt: Cancel dma map when resetting ggtt entries
drm/i915/gvt: Missed to cancel dma map for ggtt entries
...
Diffstat (limited to 'drivers')
21 files changed, 193 insertions, 135 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index f6cb502c303f..25f064c01038 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | |||
@@ -138,13 +138,6 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc) | |||
138 | lut = (struct drm_color_lut *)blob->data; | 138 | lut = (struct drm_color_lut *)blob->data; |
139 | lut_size = blob->length / sizeof(struct drm_color_lut); | 139 | lut_size = blob->length / sizeof(struct drm_color_lut); |
140 | 140 | ||
141 | if (__is_lut_linear(lut, lut_size)) { | ||
142 | /* Set to bypass if lut is set to linear */ | ||
143 | stream->out_transfer_func->type = TF_TYPE_BYPASS; | ||
144 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; | ||
145 | return 0; | ||
146 | } | ||
147 | |||
148 | gamma = dc_create_gamma(); | 141 | gamma = dc_create_gamma(); |
149 | if (!gamma) | 142 | if (!gamma) |
150 | return -ENOMEM; | 143 | return -ENOMEM; |
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index add90675fd2a..26fbeafc3c96 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | |||
@@ -4743,23 +4743,27 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) | |||
4743 | 4743 | ||
4744 | for (i=0; i < dep_table->count; i++) { | 4744 | for (i=0; i < dep_table->count; i++) { |
4745 | if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { | 4745 | if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { |
4746 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; | 4746 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; |
4747 | break; | 4747 | return; |
4748 | } | 4748 | } |
4749 | } | 4749 | } |
4750 | if (i == dep_table->count) | 4750 | if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { |
4751 | data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; | 4751 | data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; |
4752 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; | ||
4753 | } | ||
4752 | 4754 | ||
4753 | dep_table = table_info->vdd_dep_on_sclk; | 4755 | dep_table = table_info->vdd_dep_on_sclk; |
4754 | odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); | 4756 | odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); |
4755 | for (i=0; i < dep_table->count; i++) { | 4757 | for (i=0; i < dep_table->count; i++) { |
4756 | if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { | 4758 | if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { |
4757 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; | 4759 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; |
4758 | break; | 4760 | return; |
4759 | } | 4761 | } |
4760 | } | 4762 | } |
4761 | if (i == dep_table->count) | 4763 | if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { |
4762 | data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; | 4764 | data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; |
4765 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; | ||
4766 | } | ||
4763 | } | 4767 | } |
4764 | 4768 | ||
4765 | static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, | 4769 | static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h index fb696e3d06cf..2f8a3b983cce 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h | |||
@@ -412,8 +412,10 @@ typedef struct { | |||
412 | QuadraticInt_t ReservedEquation2; | 412 | QuadraticInt_t ReservedEquation2; |
413 | QuadraticInt_t ReservedEquation3; | 413 | QuadraticInt_t ReservedEquation3; |
414 | 414 | ||
415 | uint16_t MinVoltageUlvGfx; | ||
416 | uint16_t MinVoltageUlvSoc; | ||
415 | 417 | ||
416 | uint32_t Reserved[15]; | 418 | uint32_t Reserved[14]; |
417 | 419 | ||
418 | 420 | ||
419 | 421 | ||
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c b/drivers/gpu/drm/drm_dp_dual_mode_helper.c index 02a50929af67..e7f4fe2848a5 100644 --- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c +++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c | |||
@@ -350,19 +350,44 @@ int drm_dp_dual_mode_set_tmds_output(enum drm_dp_dual_mode_type type, | |||
350 | { | 350 | { |
351 | uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE; | 351 | uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE; |
352 | ssize_t ret; | 352 | ssize_t ret; |
353 | int retry; | ||
353 | 354 | ||
354 | if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) | 355 | if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) |
355 | return 0; | 356 | return 0; |
356 | 357 | ||
357 | ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_TMDS_OEN, | 358 | /* |
358 | &tmds_oen, sizeof(tmds_oen)); | 359 | * LSPCON adapters in low-power state may ignore the first write, so |
359 | if (ret) { | 360 | * read back and verify the written value a few times. |
360 | DRM_DEBUG_KMS("Failed to %s TMDS output buffers\n", | 361 | */ |
361 | enable ? "enable" : "disable"); | 362 | for (retry = 0; retry < 3; retry++) { |
362 | return ret; | 363 | uint8_t tmp; |
364 | |||
365 | ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_TMDS_OEN, | ||
366 | &tmds_oen, sizeof(tmds_oen)); | ||
367 | if (ret) { | ||
368 | DRM_DEBUG_KMS("Failed to %s TMDS output buffers (%d attempts)\n", | ||
369 | enable ? "enable" : "disable", | ||
370 | retry + 1); | ||
371 | return ret; | ||
372 | } | ||
373 | |||
374 | ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_TMDS_OEN, | ||
375 | &tmp, sizeof(tmp)); | ||
376 | if (ret) { | ||
377 | DRM_DEBUG_KMS("I2C read failed during TMDS output buffer %s (%d attempts)\n", | ||
378 | enable ? "enabling" : "disabling", | ||
379 | retry + 1); | ||
380 | return ret; | ||
381 | } | ||
382 | |||
383 | if (tmp == tmds_oen) | ||
384 | return 0; | ||
363 | } | 385 | } |
364 | 386 | ||
365 | return 0; | 387 | DRM_DEBUG_KMS("I2C write value mismatch during TMDS output buffer %s\n", |
388 | enable ? "enabling" : "disabling"); | ||
389 | |||
390 | return -EIO; | ||
366 | } | 391 | } |
367 | EXPORT_SYMBOL(drm_dp_dual_mode_set_tmds_output); | 392 | EXPORT_SYMBOL(drm_dp_dual_mode_set_tmds_output); |
368 | 393 | ||
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 0faaf829f5bf..f0e79178bde6 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <drm/drm_fb_helper.h> | 18 | #include <drm/drm_fb_helper.h> |
19 | #include <drm/drm_atomic.h> | 19 | #include <drm/drm_atomic.h> |
20 | #include <drm/drm_atomic_helper.h> | 20 | #include <drm/drm_atomic_helper.h> |
21 | #include <drm/drm_gem_framebuffer_helper.h> | ||
21 | #include <uapi/drm/exynos_drm.h> | 22 | #include <uapi/drm/exynos_drm.h> |
22 | 23 | ||
23 | #include "exynos_drm_drv.h" | 24 | #include "exynos_drm_drv.h" |
@@ -26,20 +27,6 @@ | |||
26 | #include "exynos_drm_iommu.h" | 27 | #include "exynos_drm_iommu.h" |
27 | #include "exynos_drm_crtc.h" | 28 | #include "exynos_drm_crtc.h" |
28 | 29 | ||
29 | #define to_exynos_fb(x) container_of(x, struct exynos_drm_fb, fb) | ||
30 | |||
31 | /* | ||
32 | * exynos specific framebuffer structure. | ||
33 | * | ||
34 | * @fb: drm framebuffer obejct. | ||
35 | * @exynos_gem: array of exynos specific gem object containing a gem object. | ||
36 | */ | ||
37 | struct exynos_drm_fb { | ||
38 | struct drm_framebuffer fb; | ||
39 | struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; | ||
40 | dma_addr_t dma_addr[MAX_FB_BUFFER]; | ||
41 | }; | ||
42 | |||
43 | static int check_fb_gem_memory_type(struct drm_device *drm_dev, | 30 | static int check_fb_gem_memory_type(struct drm_device *drm_dev, |
44 | struct exynos_drm_gem *exynos_gem) | 31 | struct exynos_drm_gem *exynos_gem) |
45 | { | 32 | { |
@@ -66,40 +53,9 @@ static int check_fb_gem_memory_type(struct drm_device *drm_dev, | |||
66 | return 0; | 53 | return 0; |
67 | } | 54 | } |
68 | 55 | ||
69 | static void exynos_drm_fb_destroy(struct drm_framebuffer *fb) | ||
70 | { | ||
71 | struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); | ||
72 | unsigned int i; | ||
73 | |||
74 | drm_framebuffer_cleanup(fb); | ||
75 | |||
76 | for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem); i++) { | ||
77 | struct drm_gem_object *obj; | ||
78 | |||
79 | if (exynos_fb->exynos_gem[i] == NULL) | ||
80 | continue; | ||
81 | |||
82 | obj = &exynos_fb->exynos_gem[i]->base; | ||
83 | drm_gem_object_unreference_unlocked(obj); | ||
84 | } | ||
85 | |||
86 | kfree(exynos_fb); | ||
87 | exynos_fb = NULL; | ||
88 | } | ||
89 | |||
90 | static int exynos_drm_fb_create_handle(struct drm_framebuffer *fb, | ||
91 | struct drm_file *file_priv, | ||
92 | unsigned int *handle) | ||
93 | { | ||
94 | struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); | ||
95 | |||
96 | return drm_gem_handle_create(file_priv, | ||
97 | &exynos_fb->exynos_gem[0]->base, handle); | ||
98 | } | ||
99 | |||
100 | static const struct drm_framebuffer_funcs exynos_drm_fb_funcs = { | 56 | static const struct drm_framebuffer_funcs exynos_drm_fb_funcs = { |
101 | .destroy = exynos_drm_fb_destroy, | 57 | .destroy = drm_gem_fb_destroy, |
102 | .create_handle = exynos_drm_fb_create_handle, | 58 | .create_handle = drm_gem_fb_create_handle, |
103 | }; | 59 | }; |
104 | 60 | ||
105 | struct drm_framebuffer * | 61 | struct drm_framebuffer * |
@@ -108,12 +64,12 @@ exynos_drm_framebuffer_init(struct drm_device *dev, | |||
108 | struct exynos_drm_gem **exynos_gem, | 64 | struct exynos_drm_gem **exynos_gem, |
109 | int count) | 65 | int count) |
110 | { | 66 | { |
111 | struct exynos_drm_fb *exynos_fb; | 67 | struct drm_framebuffer *fb; |
112 | int i; | 68 | int i; |
113 | int ret; | 69 | int ret; |
114 | 70 | ||
115 | exynos_fb = kzalloc(sizeof(*exynos_fb), GFP_KERNEL); | 71 | fb = kzalloc(sizeof(*fb), GFP_KERNEL); |
116 | if (!exynos_fb) | 72 | if (!fb) |
117 | return ERR_PTR(-ENOMEM); | 73 | return ERR_PTR(-ENOMEM); |
118 | 74 | ||
119 | for (i = 0; i < count; i++) { | 75 | for (i = 0; i < count; i++) { |
@@ -121,23 +77,21 @@ exynos_drm_framebuffer_init(struct drm_device *dev, | |||
121 | if (ret < 0) | 77 | if (ret < 0) |
122 | goto err; | 78 | goto err; |
123 | 79 | ||
124 | exynos_fb->exynos_gem[i] = exynos_gem[i]; | 80 | fb->obj[i] = &exynos_gem[i]->base; |
125 | exynos_fb->dma_addr[i] = exynos_gem[i]->dma_addr | ||
126 | + mode_cmd->offsets[i]; | ||
127 | } | 81 | } |
128 | 82 | ||
129 | drm_helper_mode_fill_fb_struct(dev, &exynos_fb->fb, mode_cmd); | 83 | drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); |
130 | 84 | ||
131 | ret = drm_framebuffer_init(dev, &exynos_fb->fb, &exynos_drm_fb_funcs); | 85 | ret = drm_framebuffer_init(dev, fb, &exynos_drm_fb_funcs); |
132 | if (ret < 0) { | 86 | if (ret < 0) { |
133 | DRM_ERROR("failed to initialize framebuffer\n"); | 87 | DRM_ERROR("failed to initialize framebuffer\n"); |
134 | goto err; | 88 | goto err; |
135 | } | 89 | } |
136 | 90 | ||
137 | return &exynos_fb->fb; | 91 | return fb; |
138 | 92 | ||
139 | err: | 93 | err: |
140 | kfree(exynos_fb); | 94 | kfree(fb); |
141 | return ERR_PTR(ret); | 95 | return ERR_PTR(ret); |
142 | } | 96 | } |
143 | 97 | ||
@@ -191,12 +145,13 @@ err: | |||
191 | 145 | ||
192 | dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index) | 146 | dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index) |
193 | { | 147 | { |
194 | struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); | 148 | struct exynos_drm_gem *exynos_gem; |
195 | 149 | ||
196 | if (WARN_ON_ONCE(index >= MAX_FB_BUFFER)) | 150 | if (WARN_ON_ONCE(index >= MAX_FB_BUFFER)) |
197 | return 0; | 151 | return 0; |
198 | 152 | ||
199 | return exynos_fb->dma_addr[index]; | 153 | exynos_gem = to_exynos_gem(fb->obj[index]); |
154 | return exynos_gem->dma_addr + fb->offsets[index]; | ||
200 | } | 155 | } |
201 | 156 | ||
202 | static struct drm_mode_config_helper_funcs exynos_drm_mode_config_helpers = { | 157 | static struct drm_mode_config_helper_funcs exynos_drm_mode_config_helpers = { |
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index db6b94dda5df..d85939bd7b47 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c | |||
@@ -1080,6 +1080,7 @@ static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) | |||
1080 | { | 1080 | { |
1081 | set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt, | 1081 | set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt, |
1082 | s->workload->pending_events); | 1082 | s->workload->pending_events); |
1083 | patch_value(s, cmd_ptr(s, 0), MI_NOOP); | ||
1083 | return 0; | 1084 | return 0; |
1084 | } | 1085 | } |
1085 | 1086 | ||
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index dd96ffc878ac..6d8180e8d1e2 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c | |||
@@ -169,6 +169,8 @@ static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { | |||
169 | static void emulate_monitor_status_change(struct intel_vgpu *vgpu) | 169 | static void emulate_monitor_status_change(struct intel_vgpu *vgpu) |
170 | { | 170 | { |
171 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | 171 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; |
172 | int pipe; | ||
173 | |||
172 | vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | | 174 | vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | |
173 | SDE_PORTC_HOTPLUG_CPT | | 175 | SDE_PORTC_HOTPLUG_CPT | |
174 | SDE_PORTD_HOTPLUG_CPT); | 176 | SDE_PORTD_HOTPLUG_CPT); |
@@ -267,6 +269,14 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) | |||
267 | if (IS_BROADWELL(dev_priv)) | 269 | if (IS_BROADWELL(dev_priv)) |
268 | vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; | 270 | vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; |
269 | 271 | ||
272 | /* Disable Primary/Sprite/Cursor plane */ | ||
273 | for_each_pipe(dev_priv, pipe) { | ||
274 | vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; | ||
275 | vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; | ||
276 | vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~CURSOR_MODE; | ||
277 | vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= CURSOR_MODE_DISABLE; | ||
278 | } | ||
279 | |||
270 | vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; | 280 | vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; |
271 | } | 281 | } |
272 | 282 | ||
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index b555eb26f9ce..6f4f8e941fc2 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c | |||
@@ -323,6 +323,7 @@ static void update_fb_info(struct vfio_device_gfx_plane_info *gvt_dmabuf, | |||
323 | struct intel_vgpu_fb_info *fb_info) | 323 | struct intel_vgpu_fb_info *fb_info) |
324 | { | 324 | { |
325 | gvt_dmabuf->drm_format = fb_info->drm_format; | 325 | gvt_dmabuf->drm_format = fb_info->drm_format; |
326 | gvt_dmabuf->drm_format_mod = fb_info->drm_format_mod; | ||
326 | gvt_dmabuf->width = fb_info->width; | 327 | gvt_dmabuf->width = fb_info->width; |
327 | gvt_dmabuf->height = fb_info->height; | 328 | gvt_dmabuf->height = fb_info->height; |
328 | gvt_dmabuf->stride = fb_info->stride; | 329 | gvt_dmabuf->stride = fb_info->stride; |
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 6b50fe78dc1b..1c120683e958 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c | |||
@@ -245,16 +245,13 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, | |||
245 | plane->hw_format = fmt; | 245 | plane->hw_format = fmt; |
246 | 246 | ||
247 | plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; | 247 | plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; |
248 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { | 248 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) |
249 | gvt_vgpu_err("invalid gma address: %lx\n", | ||
250 | (unsigned long)plane->base); | ||
251 | return -EINVAL; | 249 | return -EINVAL; |
252 | } | ||
253 | 250 | ||
254 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); | 251 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); |
255 | if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { | 252 | if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { |
256 | gvt_vgpu_err("invalid gma address: %lx\n", | 253 | gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", |
257 | (unsigned long)plane->base); | 254 | plane->base); |
258 | return -EINVAL; | 255 | return -EINVAL; |
259 | } | 256 | } |
260 | 257 | ||
@@ -371,16 +368,13 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, | |||
371 | alpha_plane, alpha_force); | 368 | alpha_plane, alpha_force); |
372 | 369 | ||
373 | plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; | 370 | plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; |
374 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { | 371 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) |
375 | gvt_vgpu_err("invalid gma address: %lx\n", | ||
376 | (unsigned long)plane->base); | ||
377 | return -EINVAL; | 372 | return -EINVAL; |
378 | } | ||
379 | 373 | ||
380 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); | 374 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); |
381 | if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { | 375 | if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { |
382 | gvt_vgpu_err("invalid gma address: %lx\n", | 376 | gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", |
383 | (unsigned long)plane->base); | 377 | plane->base); |
384 | return -EINVAL; | 378 | return -EINVAL; |
385 | } | 379 | } |
386 | 380 | ||
@@ -476,16 +470,13 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, | |||
476 | plane->drm_format = drm_format; | 470 | plane->drm_format = drm_format; |
477 | 471 | ||
478 | plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; | 472 | plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; |
479 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) { | 473 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) |
480 | gvt_vgpu_err("invalid gma address: %lx\n", | ||
481 | (unsigned long)plane->base); | ||
482 | return -EINVAL; | 474 | return -EINVAL; |
483 | } | ||
484 | 475 | ||
485 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); | 476 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); |
486 | if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { | 477 | if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { |
487 | gvt_vgpu_err("invalid gma address: %lx\n", | 478 | gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", |
488 | (unsigned long)plane->base); | 479 | plane->base); |
489 | return -EINVAL; | 480 | return -EINVAL; |
490 | } | 481 | } |
491 | 482 | ||
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index d29281231507..78e55aafc8bc 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c | |||
@@ -530,6 +530,16 @@ static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm, | |||
530 | false, 0, mm->vgpu); | 530 | false, 0, mm->vgpu); |
531 | } | 531 | } |
532 | 532 | ||
533 | static void ggtt_get_host_entry(struct intel_vgpu_mm *mm, | ||
534 | struct intel_gvt_gtt_entry *entry, unsigned long index) | ||
535 | { | ||
536 | struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; | ||
537 | |||
538 | GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT); | ||
539 | |||
540 | pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu); | ||
541 | } | ||
542 | |||
533 | static void ggtt_set_host_entry(struct intel_vgpu_mm *mm, | 543 | static void ggtt_set_host_entry(struct intel_vgpu_mm *mm, |
534 | struct intel_gvt_gtt_entry *entry, unsigned long index) | 544 | struct intel_gvt_gtt_entry *entry, unsigned long index) |
535 | { | 545 | { |
@@ -1818,6 +1828,18 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off, | |||
1818 | return ret; | 1828 | return ret; |
1819 | } | 1829 | } |
1820 | 1830 | ||
1831 | static void ggtt_invalidate_pte(struct intel_vgpu *vgpu, | ||
1832 | struct intel_gvt_gtt_entry *entry) | ||
1833 | { | ||
1834 | struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops; | ||
1835 | unsigned long pfn; | ||
1836 | |||
1837 | pfn = pte_ops->get_pfn(entry); | ||
1838 | if (pfn != vgpu->gvt->gtt.scratch_mfn) | ||
1839 | intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, | ||
1840 | pfn << PAGE_SHIFT); | ||
1841 | } | ||
1842 | |||
1821 | static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, | 1843 | static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, |
1822 | void *p_data, unsigned int bytes) | 1844 | void *p_data, unsigned int bytes) |
1823 | { | 1845 | { |
@@ -1844,10 +1866,10 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, | |||
1844 | 1866 | ||
1845 | memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data, | 1867 | memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data, |
1846 | bytes); | 1868 | bytes); |
1847 | m = e; | ||
1848 | 1869 | ||
1849 | if (ops->test_present(&e)) { | 1870 | if (ops->test_present(&e)) { |
1850 | gfn = ops->get_pfn(&e); | 1871 | gfn = ops->get_pfn(&e); |
1872 | m = e; | ||
1851 | 1873 | ||
1852 | /* one PTE update may be issued in multiple writes and the | 1874 | /* one PTE update may be issued in multiple writes and the |
1853 | * first write may not construct a valid gfn | 1875 | * first write may not construct a valid gfn |
@@ -1868,8 +1890,12 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, | |||
1868 | ops->set_pfn(&m, gvt->gtt.scratch_mfn); | 1890 | ops->set_pfn(&m, gvt->gtt.scratch_mfn); |
1869 | } else | 1891 | } else |
1870 | ops->set_pfn(&m, dma_addr >> PAGE_SHIFT); | 1892 | ops->set_pfn(&m, dma_addr >> PAGE_SHIFT); |
1871 | } else | 1893 | } else { |
1894 | ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index); | ||
1895 | ggtt_invalidate_pte(vgpu, &m); | ||
1872 | ops->set_pfn(&m, gvt->gtt.scratch_mfn); | 1896 | ops->set_pfn(&m, gvt->gtt.scratch_mfn); |
1897 | ops->clear_present(&m); | ||
1898 | } | ||
1873 | 1899 | ||
1874 | out: | 1900 | out: |
1875 | ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index); | 1901 | ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index); |
@@ -2030,7 +2056,7 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu) | |||
2030 | return PTR_ERR(gtt->ggtt_mm); | 2056 | return PTR_ERR(gtt->ggtt_mm); |
2031 | } | 2057 | } |
2032 | 2058 | ||
2033 | intel_vgpu_reset_ggtt(vgpu); | 2059 | intel_vgpu_reset_ggtt(vgpu, false); |
2034 | 2060 | ||
2035 | return create_scratch_page_tree(vgpu); | 2061 | return create_scratch_page_tree(vgpu); |
2036 | } | 2062 | } |
@@ -2315,17 +2341,19 @@ void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu) | |||
2315 | /** | 2341 | /** |
2316 | * intel_vgpu_reset_ggtt - reset the GGTT entry | 2342 | * intel_vgpu_reset_ggtt - reset the GGTT entry |
2317 | * @vgpu: a vGPU | 2343 | * @vgpu: a vGPU |
2344 | * @invalidate_old: invalidate old entries | ||
2318 | * | 2345 | * |
2319 | * This function is called at the vGPU create stage | 2346 | * This function is called at the vGPU create stage |
2320 | * to reset all the GGTT entries. | 2347 | * to reset all the GGTT entries. |
2321 | * | 2348 | * |
2322 | */ | 2349 | */ |
2323 | void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) | 2350 | void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old) |
2324 | { | 2351 | { |
2325 | struct intel_gvt *gvt = vgpu->gvt; | 2352 | struct intel_gvt *gvt = vgpu->gvt; |
2326 | struct drm_i915_private *dev_priv = gvt->dev_priv; | 2353 | struct drm_i915_private *dev_priv = gvt->dev_priv; |
2327 | struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops; | 2354 | struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops; |
2328 | struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE}; | 2355 | struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE}; |
2356 | struct intel_gvt_gtt_entry old_entry; | ||
2329 | u32 index; | 2357 | u32 index; |
2330 | u32 num_entries; | 2358 | u32 num_entries; |
2331 | 2359 | ||
@@ -2334,13 +2362,23 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) | |||
2334 | 2362 | ||
2335 | index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; | 2363 | index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; |
2336 | num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT; | 2364 | num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT; |
2337 | while (num_entries--) | 2365 | while (num_entries--) { |
2366 | if (invalidate_old) { | ||
2367 | ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index); | ||
2368 | ggtt_invalidate_pte(vgpu, &old_entry); | ||
2369 | } | ||
2338 | ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++); | 2370 | ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++); |
2371 | } | ||
2339 | 2372 | ||
2340 | index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; | 2373 | index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; |
2341 | num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT; | 2374 | num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT; |
2342 | while (num_entries--) | 2375 | while (num_entries--) { |
2376 | if (invalidate_old) { | ||
2377 | ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index); | ||
2378 | ggtt_invalidate_pte(vgpu, &old_entry); | ||
2379 | } | ||
2343 | ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++); | 2380 | ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++); |
2381 | } | ||
2344 | 2382 | ||
2345 | ggtt_invalidate(dev_priv); | 2383 | ggtt_invalidate(dev_priv); |
2346 | } | 2384 | } |
@@ -2360,5 +2398,5 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu) | |||
2360 | * removing the shadow pages. | 2398 | * removing the shadow pages. |
2361 | */ | 2399 | */ |
2362 | intel_vgpu_destroy_all_ppgtt_mm(vgpu); | 2400 | intel_vgpu_destroy_all_ppgtt_mm(vgpu); |
2363 | intel_vgpu_reset_ggtt(vgpu); | 2401 | intel_vgpu_reset_ggtt(vgpu, true); |
2364 | } | 2402 | } |
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index a8b369cd352b..3792f2b7f4ff 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h | |||
@@ -193,7 +193,7 @@ struct intel_vgpu_gtt { | |||
193 | 193 | ||
194 | extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); | 194 | extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); |
195 | extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); | 195 | extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); |
196 | void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu); | 196 | void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old); |
197 | void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); | 197 | void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); |
198 | 198 | ||
199 | extern int intel_gvt_init_gtt(struct intel_gvt *gvt); | 199 | extern int intel_gvt_init_gtt(struct intel_gvt *gvt); |
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 8c5d5d005854..a33c1c3e4a21 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c | |||
@@ -1150,6 +1150,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) | |||
1150 | switch (notification) { | 1150 | switch (notification) { |
1151 | case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: | 1151 | case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: |
1152 | root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; | 1152 | root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; |
1153 | /* fall through */ | ||
1153 | case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: | 1154 | case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: |
1154 | mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); | 1155 | mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); |
1155 | return PTR_ERR_OR_ZERO(mm); | 1156 | return PTR_ERR_OR_ZERO(mm); |
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index c16a492449d7..1466d8769ec9 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c | |||
@@ -1301,7 +1301,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd, | |||
1301 | 1301 | ||
1302 | } | 1302 | } |
1303 | 1303 | ||
1304 | return 0; | 1304 | return -ENOTTY; |
1305 | } | 1305 | } |
1306 | 1306 | ||
1307 | static ssize_t | 1307 | static ssize_t |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 84ca369f15a5..3b4daafebdcb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -1105,30 +1105,32 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |||
1105 | 1105 | ||
1106 | ret = i915_ggtt_probe_hw(dev_priv); | 1106 | ret = i915_ggtt_probe_hw(dev_priv); |
1107 | if (ret) | 1107 | if (ret) |
1108 | return ret; | 1108 | goto err_perf; |
1109 | 1109 | ||
1110 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, | 1110 | /* |
1111 | * otherwise the vga fbdev driver falls over. */ | 1111 | * WARNING: Apparently we must kick fbdev drivers before vgacon, |
1112 | * otherwise the vga fbdev driver falls over. | ||
1113 | */ | ||
1112 | ret = i915_kick_out_firmware_fb(dev_priv); | 1114 | ret = i915_kick_out_firmware_fb(dev_priv); |
1113 | if (ret) { | 1115 | if (ret) { |
1114 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); | 1116 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); |
1115 | goto out_ggtt; | 1117 | goto err_ggtt; |
1116 | } | 1118 | } |
1117 | 1119 | ||
1118 | ret = i915_kick_out_vgacon(dev_priv); | 1120 | ret = i915_kick_out_vgacon(dev_priv); |
1119 | if (ret) { | 1121 | if (ret) { |
1120 | DRM_ERROR("failed to remove conflicting VGA console\n"); | 1122 | DRM_ERROR("failed to remove conflicting VGA console\n"); |
1121 | goto out_ggtt; | 1123 | goto err_ggtt; |
1122 | } | 1124 | } |
1123 | 1125 | ||
1124 | ret = i915_ggtt_init_hw(dev_priv); | 1126 | ret = i915_ggtt_init_hw(dev_priv); |
1125 | if (ret) | 1127 | if (ret) |
1126 | return ret; | 1128 | goto err_ggtt; |
1127 | 1129 | ||
1128 | ret = i915_ggtt_enable_hw(dev_priv); | 1130 | ret = i915_ggtt_enable_hw(dev_priv); |
1129 | if (ret) { | 1131 | if (ret) { |
1130 | DRM_ERROR("failed to enable GGTT\n"); | 1132 | DRM_ERROR("failed to enable GGTT\n"); |
1131 | goto out_ggtt; | 1133 | goto err_ggtt; |
1132 | } | 1134 | } |
1133 | 1135 | ||
1134 | pci_set_master(pdev); | 1136 | pci_set_master(pdev); |
@@ -1139,7 +1141,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |||
1139 | if (ret) { | 1141 | if (ret) { |
1140 | DRM_ERROR("failed to set DMA mask\n"); | 1142 | DRM_ERROR("failed to set DMA mask\n"); |
1141 | 1143 | ||
1142 | goto out_ggtt; | 1144 | goto err_ggtt; |
1143 | } | 1145 | } |
1144 | } | 1146 | } |
1145 | 1147 | ||
@@ -1157,7 +1159,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |||
1157 | if (ret) { | 1159 | if (ret) { |
1158 | DRM_ERROR("failed to set DMA mask\n"); | 1160 | DRM_ERROR("failed to set DMA mask\n"); |
1159 | 1161 | ||
1160 | goto out_ggtt; | 1162 | goto err_ggtt; |
1161 | } | 1163 | } |
1162 | } | 1164 | } |
1163 | 1165 | ||
@@ -1190,13 +1192,14 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) | |||
1190 | 1192 | ||
1191 | ret = intel_gvt_init(dev_priv); | 1193 | ret = intel_gvt_init(dev_priv); |
1192 | if (ret) | 1194 | if (ret) |
1193 | goto out_ggtt; | 1195 | goto err_ggtt; |
1194 | 1196 | ||
1195 | return 0; | 1197 | return 0; |
1196 | 1198 | ||
1197 | out_ggtt: | 1199 | err_ggtt: |
1198 | i915_ggtt_cleanup_hw(dev_priv); | 1200 | i915_ggtt_cleanup_hw(dev_priv); |
1199 | 1201 | err_perf: | |
1202 | i915_perf_fini(dev_priv); | ||
1200 | return ret; | 1203 | return ret; |
1201 | } | 1204 | } |
1202 | 1205 | ||
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 8c170db8495d..0414228cd2b5 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c | |||
@@ -728,7 +728,7 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) | |||
728 | 728 | ||
729 | err = radix_tree_insert(handles_vma, handle, vma); | 729 | err = radix_tree_insert(handles_vma, handle, vma); |
730 | if (unlikely(err)) { | 730 | if (unlikely(err)) { |
731 | kfree(lut); | 731 | kmem_cache_free(eb->i915->luts, lut); |
732 | goto err_obj; | 732 | goto err_obj; |
733 | } | 733 | } |
734 | 734 | ||
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index d8feb9053e0c..f0519e31543a 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c | |||
@@ -473,20 +473,37 @@ static u64 get_rc6(struct drm_i915_private *i915) | |||
473 | spin_lock_irqsave(&i915->pmu.lock, flags); | 473 | spin_lock_irqsave(&i915->pmu.lock, flags); |
474 | spin_lock(&kdev->power.lock); | 474 | spin_lock(&kdev->power.lock); |
475 | 475 | ||
476 | if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) | 476 | /* |
477 | i915->pmu.suspended_jiffies_last = | 477 | * After the above branch intel_runtime_pm_get_if_in_use failed |
478 | kdev->power.suspended_jiffies; | 478 | * to get the runtime PM reference we cannot assume we are in |
479 | * runtime suspend since we can either: a) race with coming out | ||
480 | * of it before we took the power.lock, or b) there are other | ||
481 | * states than suspended which can bring us here. | ||
482 | * | ||
483 | * We need to double-check that we are indeed currently runtime | ||
484 | * suspended and if not we cannot do better than report the last | ||
485 | * known RC6 value. | ||
486 | */ | ||
487 | if (kdev->power.runtime_status == RPM_SUSPENDED) { | ||
488 | if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) | ||
489 | i915->pmu.suspended_jiffies_last = | ||
490 | kdev->power.suspended_jiffies; | ||
479 | 491 | ||
480 | val = kdev->power.suspended_jiffies - | 492 | val = kdev->power.suspended_jiffies - |
481 | i915->pmu.suspended_jiffies_last; | 493 | i915->pmu.suspended_jiffies_last; |
482 | val += jiffies - kdev->power.accounting_timestamp; | 494 | val += jiffies - kdev->power.accounting_timestamp; |
483 | 495 | ||
484 | spin_unlock(&kdev->power.lock); | 496 | val = jiffies_to_nsecs(val); |
497 | val += i915->pmu.sample[__I915_SAMPLE_RC6].cur; | ||
485 | 498 | ||
486 | val = jiffies_to_nsecs(val); | 499 | i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val; |
487 | val += i915->pmu.sample[__I915_SAMPLE_RC6].cur; | 500 | } else if (i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) { |
488 | i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val; | 501 | val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur; |
502 | } else { | ||
503 | val = i915->pmu.sample[__I915_SAMPLE_RC6].cur; | ||
504 | } | ||
489 | 505 | ||
506 | spin_unlock(&kdev->power.lock); | ||
490 | spin_unlock_irqrestore(&i915->pmu.lock, flags); | 507 | spin_unlock_irqrestore(&i915->pmu.lock, flags); |
491 | } | 508 | } |
492 | 509 | ||
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 709d6ca68074..3ea566f99450 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c | |||
@@ -729,7 +729,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, | |||
729 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); | 729 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
730 | u32 tmp; | 730 | u32 tmp; |
731 | 731 | ||
732 | if (!IS_GEN9_BC(dev_priv)) | 732 | if (!IS_GEN9(dev_priv)) |
733 | return; | 733 | return; |
734 | 734 | ||
735 | i915_audio_component_get_power(kdev); | 735 | i915_audio_component_get_power(kdev); |
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index c5c7530ba157..447b721c3be9 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c | |||
@@ -1256,7 +1256,6 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, | |||
1256 | return; | 1256 | return; |
1257 | 1257 | ||
1258 | aux_channel = child->aux_channel; | 1258 | aux_channel = child->aux_channel; |
1259 | ddc_pin = child->ddc_pin; | ||
1260 | 1259 | ||
1261 | is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; | 1260 | is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; |
1262 | is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | 1261 | is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; |
@@ -1303,9 +1302,15 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, | |||
1303 | DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); | 1302 | DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); |
1304 | 1303 | ||
1305 | if (is_dvi) { | 1304 | if (is_dvi) { |
1306 | info->alternate_ddc_pin = map_ddc_pin(dev_priv, ddc_pin); | 1305 | ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin); |
1307 | 1306 | if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) { | |
1308 | sanitize_ddc_pin(dev_priv, port); | 1307 | info->alternate_ddc_pin = ddc_pin; |
1308 | sanitize_ddc_pin(dev_priv, port); | ||
1309 | } else { | ||
1310 | DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, " | ||
1311 | "sticking to defaults\n", | ||
1312 | port_name(port), ddc_pin); | ||
1313 | } | ||
1309 | } | 1314 | } |
1310 | 1315 | ||
1311 | if (is_dp) { | 1316 | if (is_dp) { |
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 697af5add78b..e3a5f673ff67 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c | |||
@@ -577,6 +577,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) | |||
577 | * know the next preemption status we see corresponds | 577 | * know the next preemption status we see corresponds |
578 | * to this ELSP update. | 578 | * to this ELSP update. |
579 | */ | 579 | */ |
580 | GEM_BUG_ON(!execlists_is_active(execlists, | ||
581 | EXECLISTS_ACTIVE_USER)); | ||
580 | GEM_BUG_ON(!port_count(&port[0])); | 582 | GEM_BUG_ON(!port_count(&port[0])); |
581 | if (port_count(&port[0]) > 1) | 583 | if (port_count(&port[0]) > 1) |
582 | goto unlock; | 584 | goto unlock; |
@@ -738,6 +740,8 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) | |||
738 | memset(port, 0, sizeof(*port)); | 740 | memset(port, 0, sizeof(*port)); |
739 | port++; | 741 | port++; |
740 | } | 742 | } |
743 | |||
744 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); | ||
741 | } | 745 | } |
742 | 746 | ||
743 | static void execlists_cancel_requests(struct intel_engine_cs *engine) | 747 | static void execlists_cancel_requests(struct intel_engine_cs *engine) |
@@ -1001,6 +1005,11 @@ static void execlists_submission_tasklet(unsigned long data) | |||
1001 | 1005 | ||
1002 | if (fw) | 1006 | if (fw) |
1003 | intel_uncore_forcewake_put(dev_priv, execlists->fw_domains); | 1007 | intel_uncore_forcewake_put(dev_priv, execlists->fw_domains); |
1008 | |||
1009 | /* If the engine is now idle, so should be the flag; and vice versa. */ | ||
1010 | GEM_BUG_ON(execlists_is_active(&engine->execlists, | ||
1011 | EXECLISTS_ACTIVE_USER) == | ||
1012 | !port_isset(engine->execlists.port)); | ||
1004 | } | 1013 | } |
1005 | 1014 | ||
1006 | static void queue_request(struct intel_engine_cs *engine, | 1015 | static void queue_request(struct intel_engine_cs *engine, |
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c index 2decc8e2c79f..add9cc97a3b6 100644 --- a/drivers/gpu/drm/vc4/vc4_bo.c +++ b/drivers/gpu/drm/vc4/vc4_bo.c | |||
@@ -195,6 +195,7 @@ static void vc4_bo_destroy(struct vc4_bo *bo) | |||
195 | vc4_bo_set_label(obj, -1); | 195 | vc4_bo_set_label(obj, -1); |
196 | 196 | ||
197 | if (bo->validated_shader) { | 197 | if (bo->validated_shader) { |
198 | kfree(bo->validated_shader->uniform_addr_offsets); | ||
198 | kfree(bo->validated_shader->texture_samples); | 199 | kfree(bo->validated_shader->texture_samples); |
199 | kfree(bo->validated_shader); | 200 | kfree(bo->validated_shader); |
200 | bo->validated_shader = NULL; | 201 | bo->validated_shader = NULL; |
@@ -591,6 +592,7 @@ void vc4_free_object(struct drm_gem_object *gem_bo) | |||
591 | } | 592 | } |
592 | 593 | ||
593 | if (bo->validated_shader) { | 594 | if (bo->validated_shader) { |
595 | kfree(bo->validated_shader->uniform_addr_offsets); | ||
594 | kfree(bo->validated_shader->texture_samples); | 596 | kfree(bo->validated_shader->texture_samples); |
595 | kfree(bo->validated_shader); | 597 | kfree(bo->validated_shader); |
596 | bo->validated_shader = NULL; | 598 | bo->validated_shader = NULL; |
diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c index d3f15bf60900..7cf82b071de2 100644 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c | |||
@@ -942,6 +942,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) | |||
942 | fail: | 942 | fail: |
943 | kfree(validation_state.branch_targets); | 943 | kfree(validation_state.branch_targets); |
944 | if (validated_shader) { | 944 | if (validated_shader) { |
945 | kfree(validated_shader->uniform_addr_offsets); | ||
945 | kfree(validated_shader->texture_samples); | 946 | kfree(validated_shader->texture_samples); |
946 | kfree(validated_shader); | 947 | kfree(validated_shader); |
947 | } | 948 | } |