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authorArchit Taneja <architt@codeaurora.org>2015-10-09 05:51:12 -0400
committerRob Clark <robdclark@gmail.com>2015-12-14 10:40:30 -0500
commit6e0eb52eba9e2c8d56e4e6826faa2bd6fd5dcf0c (patch)
tree9104ef743f22ed60be9a791e5017eb935c8a4308 /drivers
parent31c92767aef63501da0214da9736cf60ac684f20 (diff)
drm/msm/dsi: Parse bus clocks from a list
DSI bus clocks seem to vary between different DSI host versions, and the SOC to which they belong. Even the enable/disable sequence varies. Provide a list of bus clock names in dsi_cfg. The driver will use this to retrieve the clocks, and enable/disable them. Add bus clock lists for DSI6G, and DSI for MSM8916(this is DSI6G too, but there is no MMSS_CC specific clock since there is no MMSS clock controller on 8916). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.h1
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_cfg.c16
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_cfg.h2
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_host.c107
4 files changed, 53 insertions, 73 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 8140e8b820e4..7336b55d05cc 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -36,6 +36,7 @@ enum msm_dsi_phy_type {
36}; 36};
37 37
38#define DSI_DEV_REGULATOR_MAX 8 38#define DSI_DEV_REGULATOR_MAX 8
39#define DSI_BUS_CLK_MAX 4
39 40
40/* Regulators for DSI devices */ 41/* Regulators for DSI devices */
41struct dsi_reg_entry { 42struct dsi_reg_entry {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 5872d5e5934f..c40044f8a6c0 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -18,6 +18,10 @@ static const struct msm_dsi_config dsi_v2_cfg = {
18 .io_offset = 0, 18 .io_offset = 0,
19}; 19};
20 20
21static const char * const dsi_6g_bus_clk_names[] = {
22 "mdp_core_clk", "iface_clk", "bus_clk", "core_mmss_clk",
23};
24
21static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = { 25static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
22 .io_offset = DSI_6G_REG_SHIFT, 26 .io_offset = DSI_6G_REG_SHIFT,
23 .reg_cfg = { 27 .reg_cfg = {
@@ -29,6 +33,12 @@ static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
29 {"vddio", 1800000, 1800000, 100000, 100}, 33 {"vddio", 1800000, 1800000, 100000, 100},
30 }, 34 },
31 }, 35 },
36 .bus_clk_names = dsi_6g_bus_clk_names,
37 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
38};
39
40static const char * const dsi_8916_bus_clk_names[] = {
41 "mdp_core_clk", "iface_clk", "bus_clk",
32}; 42};
33 43
34static const struct msm_dsi_config msm8916_dsi_cfg = { 44static const struct msm_dsi_config msm8916_dsi_cfg = {
@@ -42,6 +52,8 @@ static const struct msm_dsi_config msm8916_dsi_cfg = {
42 {"vddio", 1800000, 1800000, 100000, 100}, 52 {"vddio", 1800000, 1800000, 100000, 100},
43 }, 53 },
44 }, 54 },
55 .bus_clk_names = dsi_8916_bus_clk_names,
56 .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
45}; 57};
46 58
47static const struct msm_dsi_config msm8994_dsi_cfg = { 59static const struct msm_dsi_config msm8994_dsi_cfg = {
@@ -57,7 +69,9 @@ static const struct msm_dsi_config msm8994_dsi_cfg = {
57 {"lab_reg", -1, -1, -1, -1}, 69 {"lab_reg", -1, -1, -1, -1},
58 {"ibb_reg", -1, -1, -1, -1}, 70 {"ibb_reg", -1, -1, -1, -1},
59 }, 71 },
60 } 72 },
73 .bus_clk_names = dsi_6g_bus_clk_names,
74 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
61}; 75};
62 76
63static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { 77static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 4cf887240177..5a36836dd6fc 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -30,6 +30,8 @@
30struct msm_dsi_config { 30struct msm_dsi_config {
31 u32 io_offset; 31 u32 io_offset;
32 struct dsi_reg_config reg_cfg; 32 struct dsi_reg_config reg_cfg;
33 const char * const *bus_clk_names;
34 const int num_bus_clks;
33}; 35};
34 36
35struct msm_dsi_cfg_handler { 37struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index f78702472819..56c75354fe03 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -103,10 +103,9 @@ struct msm_dsi_host {
103 103
104 void __iomem *ctrl_base; 104 void __iomem *ctrl_base;
105 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 105 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
106 struct clk *mdp_core_clk; 106
107 struct clk *ahb_clk; 107 struct clk *bus_clks[DSI_BUS_CLK_MAX];
108 struct clk *axi_clk; 108
109 struct clk *mmss_misc_ahb_clk;
110 struct clk *byte_clk; 109 struct clk *byte_clk;
111 struct clk *esc_clk; 110 struct clk *esc_clk;
112 struct clk *pixel_clk; 111 struct clk *pixel_clk;
@@ -319,40 +318,22 @@ static int dsi_regulator_init(struct msm_dsi_host *msm_host)
319static int dsi_clk_init(struct msm_dsi_host *msm_host) 318static int dsi_clk_init(struct msm_dsi_host *msm_host)
320{ 319{
321 struct device *dev = &msm_host->pdev->dev; 320 struct device *dev = &msm_host->pdev->dev;
322 int ret = 0; 321 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
323 322 int i, ret = 0;
324 msm_host->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk"); 323
325 if (IS_ERR(msm_host->mdp_core_clk)) { 324 /* get bus clocks */
326 ret = PTR_ERR(msm_host->mdp_core_clk); 325 for (i = 0; i < cfg->num_bus_clks; i++) {
327 pr_err("%s: Unable to get mdp core clk. ret=%d\n", 326 msm_host->bus_clks[i] = devm_clk_get(dev,
328 __func__, ret); 327 cfg->bus_clk_names[i]);
329 goto exit; 328 if (IS_ERR(msm_host->bus_clks[i])) {
330 } 329 ret = PTR_ERR(msm_host->bus_clks[i]);
331 330 pr_err("%s: Unable to get %s, ret = %d\n",
332 msm_host->ahb_clk = devm_clk_get(dev, "iface_clk"); 331 __func__, cfg->bus_clk_names[i], ret);
333 if (IS_ERR(msm_host->ahb_clk)) { 332 goto exit;
334 ret = PTR_ERR(msm_host->ahb_clk); 333 }
335 pr_err("%s: Unable to get mdss ahb clk. ret=%d\n",
336 __func__, ret);
337 goto exit;
338 }
339
340 msm_host->axi_clk = devm_clk_get(dev, "bus_clk");
341 if (IS_ERR(msm_host->axi_clk)) {
342 ret = PTR_ERR(msm_host->axi_clk);
343 pr_err("%s: Unable to get axi bus clk. ret=%d\n",
344 __func__, ret);
345 goto exit;
346 }
347
348 msm_host->mmss_misc_ahb_clk = devm_clk_get(dev, "core_mmss_clk");
349 if (IS_ERR(msm_host->mmss_misc_ahb_clk)) {
350 ret = PTR_ERR(msm_host->mmss_misc_ahb_clk);
351 pr_err("%s: Unable to get mmss misc ahb clk. ret=%d\n",
352 __func__, ret);
353 goto exit;
354 } 334 }
355 335
336 /* get link and source clocks */
356 msm_host->byte_clk = devm_clk_get(dev, "byte_clk"); 337 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
357 if (IS_ERR(msm_host->byte_clk)) { 338 if (IS_ERR(msm_host->byte_clk)) {
358 ret = PTR_ERR(msm_host->byte_clk); 339 ret = PTR_ERR(msm_host->byte_clk);
@@ -399,55 +380,37 @@ exit:
399 380
400static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 381static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
401{ 382{
402 int ret; 383 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
384 int i, ret;
403 385
404 DBG("id=%d", msm_host->id); 386 DBG("id=%d", msm_host->id);
405 387
406 ret = clk_prepare_enable(msm_host->mdp_core_clk); 388 for (i = 0; i < cfg->num_bus_clks; i++) {
407 if (ret) { 389 ret = clk_prepare_enable(msm_host->bus_clks[i]);
408 pr_err("%s: failed to enable mdp_core_clock, %d\n", 390 if (ret) {
409 __func__, ret); 391 pr_err("%s: failed to enable bus clock %d ret %d\n",
410 goto core_clk_err; 392 __func__, i, ret);
411 } 393 goto err;
412 394 }
413 ret = clk_prepare_enable(msm_host->ahb_clk);
414 if (ret) {
415 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
416 goto ahb_clk_err;
417 }
418
419 ret = clk_prepare_enable(msm_host->axi_clk);
420 if (ret) {
421 pr_err("%s: failed to enable ahb clock, %d\n", __func__, ret);
422 goto axi_clk_err;
423 }
424
425 ret = clk_prepare_enable(msm_host->mmss_misc_ahb_clk);
426 if (ret) {
427 pr_err("%s: failed to enable mmss misc ahb clk, %d\n",
428 __func__, ret);
429 goto misc_ahb_clk_err;
430 } 395 }
431 396
432 return 0; 397 return 0;
398err:
399 for (; i > 0; i--)
400 clk_disable_unprepare(msm_host->bus_clks[i]);
433 401
434misc_ahb_clk_err:
435 clk_disable_unprepare(msm_host->axi_clk);
436axi_clk_err:
437 clk_disable_unprepare(msm_host->ahb_clk);
438ahb_clk_err:
439 clk_disable_unprepare(msm_host->mdp_core_clk);
440core_clk_err:
441 return ret; 402 return ret;
442} 403}
443 404
444static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 405static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
445{ 406{
407 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
408 int i;
409
446 DBG(""); 410 DBG("");
447 clk_disable_unprepare(msm_host->mmss_misc_ahb_clk); 411
448 clk_disable_unprepare(msm_host->axi_clk); 412 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
449 clk_disable_unprepare(msm_host->ahb_clk); 413 clk_disable_unprepare(msm_host->bus_clks[i]);
450 clk_disable_unprepare(msm_host->mdp_core_clk);
451} 414}
452 415
453static int dsi_link_clk_enable(struct msm_dsi_host *msm_host) 416static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)