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authorDave Jiang <dave.jiang@intel.com>2018-01-29 15:22:30 -0500
committerJon Mason <jdmason@kudzu.us>2018-06-11 15:20:59 -0400
commit6c1e8ab2d154852f43eb6d139821b7a85e31b21a (patch)
treec57f3ae0532cfd5958f3c9140423fea48b7c4075 /drivers
parentf6e51c354b60c177a4287f236d353b430d3dc6c1 (diff)
ntb: intel: change references of skx to gen3
Change all references to skx to gen3 NTB. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen1.c19
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen3.c144
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen3.h89
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_intel.h4
4 files changed, 126 insertions, 130 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c
index f2554ac8afac..ffdee98e8ece 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen1.c
+++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c
@@ -45,9 +45,6 @@
45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 * 46 *
47 * Intel PCIe NTB Linux driver 47 * Intel PCIe NTB Linux driver
48 *
49 * Contact Information:
50 * Jon Mason <jon.mason@intel.com>
51 */ 48 */
52 49
53#include <linux/debugfs.h> 50#include <linux/debugfs.h>
@@ -651,7 +648,7 @@ static ssize_t ndev_ntb_debugfs_read(struct file *filp, char __user *ubuf,
651 "LMT45 -\t\t\t%#018llx\n", u.v64); 648 "LMT45 -\t\t\t%#018llx\n", u.v64);
652 } 649 }
653 650
654 if (pdev_is_xeon(pdev)) { 651 if (pdev_is_gen1(pdev)) {
655 if (ntb_topo_is_b2b(ndev->ntb.topo)) { 652 if (ntb_topo_is_b2b(ndev->ntb.topo)) {
656 off += scnprintf(buf + off, buf_size - off, 653 off += scnprintf(buf + off, buf_size - off,
657 "\nNTB Outgoing B2B XLAT:\n"); 654 "\nNTB Outgoing B2B XLAT:\n");
@@ -763,9 +760,9 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
763{ 760{
764 struct intel_ntb_dev *ndev = filp->private_data; 761 struct intel_ntb_dev *ndev = filp->private_data;
765 762
766 if (pdev_is_xeon(ndev->ntb.pdev)) 763 if (pdev_is_gen1(ndev->ntb.pdev))
767 return ndev_ntb_debugfs_read(filp, ubuf, count, offp); 764 return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
768 else if (pdev_is_skx_xeon(ndev->ntb.pdev)) 765 else if (pdev_is_gen3(ndev->ntb.pdev))
769 return ndev_ntb3_debugfs_read(filp, ubuf, count, offp); 766 return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
770 767
771 return -ENXIO; 768 return -ENXIO;
@@ -1849,7 +1846,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1849 1846
1850 node = dev_to_node(&pdev->dev); 1847 node = dev_to_node(&pdev->dev);
1851 1848
1852 if (pdev_is_xeon(pdev)) { 1849 if (pdev_is_gen1(pdev)) {
1853 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); 1850 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1854 if (!ndev) { 1851 if (!ndev) {
1855 rc = -ENOMEM; 1852 rc = -ENOMEM;
@@ -1866,7 +1863,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1866 if (rc) 1863 if (rc)
1867 goto err_init_dev; 1864 goto err_init_dev;
1868 1865
1869 } else if (pdev_is_skx_xeon(pdev)) { 1866 } else if (pdev_is_gen3(pdev)) {
1870 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); 1867 ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
1871 if (!ndev) { 1868 if (!ndev) {
1872 rc = -ENOMEM; 1869 rc = -ENOMEM;
@@ -1880,7 +1877,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1880 if (rc) 1877 if (rc)
1881 goto err_init_pci; 1878 goto err_init_pci;
1882 1879
1883 rc = skx_init_dev(ndev); 1880 rc = gen3_init_dev(ndev);
1884 if (rc) 1881 if (rc)
1885 goto err_init_dev; 1882 goto err_init_dev;
1886 1883
@@ -1905,7 +1902,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
1905 1902
1906err_register: 1903err_register:
1907 ndev_deinit_debugfs(ndev); 1904 ndev_deinit_debugfs(ndev);
1908 if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev)) 1905 if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
1909 xeon_deinit_dev(ndev); 1906 xeon_deinit_dev(ndev);
1910err_init_dev: 1907err_init_dev:
1911 intel_ntb_deinit_pci(ndev); 1908 intel_ntb_deinit_pci(ndev);
@@ -1921,7 +1918,7 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev)
1921 1918
1922 ntb_unregister_device(&ndev->ntb); 1919 ntb_unregister_device(&ndev->ntb);
1923 ndev_deinit_debugfs(ndev); 1920 ndev_deinit_debugfs(ndev);
1924 if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev)) 1921 if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
1925 xeon_deinit_dev(ndev); 1922 xeon_deinit_dev(ndev);
1926 intel_ntb_deinit_pci(ndev); 1923 intel_ntb_deinit_pci(ndev);
1927 kfree(ndev); 1924 kfree(ndev);
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.c b/drivers/ntb/hw/intel/ntb_hw_gen3.c
index 52cd8cdf7697..b3fa24778f94 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen3.c
+++ b/drivers/ntb/hw/intel/ntb_hw_gen3.c
@@ -40,10 +40,8 @@
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * 42 *
43 * Intel PCIe NTB Linux driver 43 * Intel PCIe GEN3 NTB Linux driver
44 * 44 *
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
47 */ 45 */
48 46
49#include <linux/debugfs.h> 47#include <linux/debugfs.h>
@@ -60,37 +58,39 @@
60#include "ntb_hw_gen1.h" 58#include "ntb_hw_gen1.h"
61#include "ntb_hw_gen3.h" 59#include "ntb_hw_gen3.h"
62 60
63static const struct intel_ntb_reg skx_reg = { 61static int gen3_poll_link(struct intel_ntb_dev *ndev);
64 .poll_link = skx_poll_link, 62
63static const struct intel_ntb_reg gen3_reg = {
64 .poll_link = gen3_poll_link,
65 .link_is_up = xeon_link_is_up, 65 .link_is_up = xeon_link_is_up,
66 .db_ioread = skx_db_ioread, 66 .db_ioread = gen3_db_ioread,
67 .db_iowrite = skx_db_iowrite, 67 .db_iowrite = gen3_db_iowrite,
68 .db_size = sizeof(u32), 68 .db_size = sizeof(u32),
69 .ntb_ctl = SKX_NTBCNTL_OFFSET, 69 .ntb_ctl = GEN3_NTBCNTL_OFFSET,
70 .mw_bar = {2, 4}, 70 .mw_bar = {2, 4},
71}; 71};
72 72
73static const struct intel_ntb_alt_reg skx_pri_reg = { 73static const struct intel_ntb_alt_reg gen3_pri_reg = {
74 .db_bell = SKX_EM_DOORBELL_OFFSET, 74 .db_bell = GEN3_EM_DOORBELL_OFFSET,
75 .db_clear = SKX_IM_INT_STATUS_OFFSET, 75 .db_clear = GEN3_IM_INT_STATUS_OFFSET,
76 .db_mask = SKX_IM_INT_DISABLE_OFFSET, 76 .db_mask = GEN3_IM_INT_DISABLE_OFFSET,
77 .spad = SKX_IM_SPAD_OFFSET, 77 .spad = GEN3_IM_SPAD_OFFSET,
78}; 78};
79 79
80static const struct intel_ntb_alt_reg skx_b2b_reg = { 80static const struct intel_ntb_alt_reg gen3_b2b_reg = {
81 .db_bell = SKX_IM_DOORBELL_OFFSET, 81 .db_bell = GEN3_IM_DOORBELL_OFFSET,
82 .db_clear = SKX_EM_INT_STATUS_OFFSET, 82 .db_clear = GEN3_EM_INT_STATUS_OFFSET,
83 .db_mask = SKX_EM_INT_DISABLE_OFFSET, 83 .db_mask = GEN3_EM_INT_DISABLE_OFFSET,
84 .spad = SKX_B2B_SPAD_OFFSET, 84 .spad = GEN3_B2B_SPAD_OFFSET,
85}; 85};
86 86
87static const struct intel_ntb_xlat_reg skx_sec_xlat = { 87static const struct intel_ntb_xlat_reg gen3_sec_xlat = {
88/* .bar0_base = SKX_EMBAR0_OFFSET, */ 88/* .bar0_base = GEN3_EMBAR0_OFFSET, */
89 .bar2_limit = SKX_IMBAR1XLMT_OFFSET, 89 .bar2_limit = GEN3_IMBAR1XLMT_OFFSET,
90 .bar2_xlat = SKX_IMBAR1XBASE_OFFSET, 90 .bar2_xlat = GEN3_IMBAR1XBASE_OFFSET,
91}; 91};
92 92
93int skx_poll_link(struct intel_ntb_dev *ndev) 93static int gen3_poll_link(struct intel_ntb_dev *ndev)
94{ 94{
95 u16 reg_val; 95 u16 reg_val;
96 int rc; 96 int rc;
@@ -100,7 +100,7 @@ int skx_poll_link(struct intel_ntb_dev *ndev)
100 ndev->self_reg->db_clear); 100 ndev->self_reg->db_clear);
101 101
102 rc = pci_read_config_word(ndev->ntb.pdev, 102 rc = pci_read_config_word(ndev->ntb.pdev,
103 SKX_LINK_STATUS_OFFSET, &reg_val); 103 GEN3_LINK_STATUS_OFFSET, &reg_val);
104 if (rc) 104 if (rc)
105 return 0; 105 return 0;
106 106
@@ -112,7 +112,7 @@ int skx_poll_link(struct intel_ntb_dev *ndev)
112 return 1; 112 return 1;
113} 113}
114 114
115static int skx_init_isr(struct intel_ntb_dev *ndev) 115static int gen3_init_isr(struct intel_ntb_dev *ndev)
116{ 116{
117 int i; 117 int i;
118 118
@@ -123,23 +123,23 @@ static int skx_init_isr(struct intel_ntb_dev *ndev)
123 * The vectors at reset is 1-32,0. We need to reprogram to 0-32. 123 * The vectors at reset is 1-32,0. We need to reprogram to 0-32.
124 */ 124 */
125 125
126 for (i = 0; i < SKX_DB_MSIX_VECTOR_COUNT; i++) 126 for (i = 0; i < GEN3_DB_MSIX_VECTOR_COUNT; i++)
127 iowrite8(i, ndev->self_mmio + SKX_INTVEC_OFFSET + i); 127 iowrite8(i, ndev->self_mmio + GEN3_INTVEC_OFFSET + i);
128 128
129 /* move link status down one as workaround */ 129 /* move link status down one as workaround */
130 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) { 130 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) {
131 iowrite8(SKX_DB_MSIX_VECTOR_COUNT - 2, 131 iowrite8(GEN3_DB_MSIX_VECTOR_COUNT - 2,
132 ndev->self_mmio + SKX_INTVEC_OFFSET + 132 ndev->self_mmio + GEN3_INTVEC_OFFSET +
133 (SKX_DB_MSIX_VECTOR_COUNT - 1)); 133 (GEN3_DB_MSIX_VECTOR_COUNT - 1));
134 } 134 }
135 135
136 return ndev_init_isr(ndev, SKX_DB_MSIX_VECTOR_COUNT, 136 return ndev_init_isr(ndev, GEN3_DB_MSIX_VECTOR_COUNT,
137 SKX_DB_MSIX_VECTOR_COUNT, 137 GEN3_DB_MSIX_VECTOR_COUNT,
138 SKX_DB_MSIX_VECTOR_SHIFT, 138 GEN3_DB_MSIX_VECTOR_SHIFT,
139 SKX_DB_TOTAL_SHIFT); 139 GEN3_DB_TOTAL_SHIFT);
140} 140}
141 141
142static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev, 142static int gen3_setup_b2b_mw(struct intel_ntb_dev *ndev,
143 const struct intel_b2b_addr *addr, 143 const struct intel_b2b_addr *addr,
144 const struct intel_b2b_addr *peer_addr) 144 const struct intel_b2b_addr *peer_addr)
145{ 145{
@@ -152,33 +152,33 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
152 152
153 /* setup incoming bar limits == base addrs (zero length windows) */ 153 /* setup incoming bar limits == base addrs (zero length windows) */
154 bar_addr = addr->bar2_addr64; 154 bar_addr = addr->bar2_addr64;
155 iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET); 155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET);
156 bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET); 156 bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
157 dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr); 157 dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
158 158
159 bar_addr = addr->bar4_addr64; 159 bar_addr = addr->bar4_addr64;
160 iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET); 160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET);
161 bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET); 161 bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
162 dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr); 162 dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
163 163
164 /* zero incoming translation addrs */ 164 /* zero incoming translation addrs */
165 iowrite64(0, mmio + SKX_IMBAR1XBASE_OFFSET); 165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET);
166 iowrite64(0, mmio + SKX_IMBAR2XBASE_OFFSET); 166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET);
167 167
168 ndev->peer_mmio = ndev->self_mmio; 168 ndev->peer_mmio = ndev->self_mmio;
169 169
170 return 0; 170 return 0;
171} 171}
172 172
173static int skx_init_ntb(struct intel_ntb_dev *ndev) 173static int gen3_init_ntb(struct intel_ntb_dev *ndev)
174{ 174{
175 int rc; 175 int rc;
176 176
177 177
178 ndev->mw_count = XEON_MW_COUNT; 178 ndev->mw_count = XEON_MW_COUNT;
179 ndev->spad_count = SKX_SPAD_COUNT; 179 ndev->spad_count = GEN3_SPAD_COUNT;
180 ndev->db_count = SKX_DB_COUNT; 180 ndev->db_count = GEN3_DB_COUNT;
181 ndev->db_link_mask = SKX_DB_LINK_BIT; 181 ndev->db_link_mask = GEN3_DB_LINK_BIT;
182 182
183 /* DB fixup for using 31 right now */ 183 /* DB fixup for using 31 right now */
184 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) 184 if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)
@@ -187,16 +187,16 @@ static int skx_init_ntb(struct intel_ntb_dev *ndev)
187 switch (ndev->ntb.topo) { 187 switch (ndev->ntb.topo) {
188 case NTB_TOPO_B2B_USD: 188 case NTB_TOPO_B2B_USD:
189 case NTB_TOPO_B2B_DSD: 189 case NTB_TOPO_B2B_DSD:
190 ndev->self_reg = &skx_pri_reg; 190 ndev->self_reg = &gen3_pri_reg;
191 ndev->peer_reg = &skx_b2b_reg; 191 ndev->peer_reg = &gen3_b2b_reg;
192 ndev->xlat_reg = &skx_sec_xlat; 192 ndev->xlat_reg = &gen3_sec_xlat;
193 193
194 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { 194 if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
195 rc = skx_setup_b2b_mw(ndev, 195 rc = gen3_setup_b2b_mw(ndev,
196 &xeon_b2b_dsd_addr, 196 &xeon_b2b_dsd_addr,
197 &xeon_b2b_usd_addr); 197 &xeon_b2b_usd_addr);
198 } else { 198 } else {
199 rc = skx_setup_b2b_mw(ndev, 199 rc = gen3_setup_b2b_mw(ndev,
200 &xeon_b2b_usd_addr, 200 &xeon_b2b_usd_addr,
201 &xeon_b2b_dsd_addr); 201 &xeon_b2b_dsd_addr);
202 } 202 }
@@ -206,7 +206,7 @@ static int skx_init_ntb(struct intel_ntb_dev *ndev)
206 206
207 /* Enable Bus Master and Memory Space on the secondary side */ 207 /* Enable Bus Master and Memory Space on the secondary side */
208 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, 208 iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
209 ndev->self_mmio + SKX_SPCICMD_OFFSET); 209 ndev->self_mmio + GEN3_SPCICMD_OFFSET);
210 210
211 break; 211 break;
212 212
@@ -223,7 +223,7 @@ static int skx_init_ntb(struct intel_ntb_dev *ndev)
223 return 0; 223 return 0;
224} 224}
225 225
226int skx_init_dev(struct intel_ntb_dev *ndev) 226int gen3_init_dev(struct intel_ntb_dev *ndev)
227{ 227{
228 struct pci_dev *pdev; 228 struct pci_dev *pdev;
229 u8 ppd; 229 u8 ppd;
@@ -231,7 +231,7 @@ int skx_init_dev(struct intel_ntb_dev *ndev)
231 231
232 pdev = ndev->ntb.pdev; 232 pdev = ndev->ntb.pdev;
233 233
234 ndev->reg = &skx_reg; 234 ndev->reg = &gen3_reg;
235 235
236 rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd); 236 rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
237 if (rc) 237 if (rc)
@@ -245,11 +245,11 @@ int skx_init_dev(struct intel_ntb_dev *ndev)
245 245
246 ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD; 246 ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;
247 247
248 rc = skx_init_ntb(ndev); 248 rc = gen3_init_ntb(ndev);
249 if (rc) 249 if (rc)
250 return rc; 250 return rc;
251 251
252 return skx_init_isr(ndev); 252 return gen3_init_isr(ndev);
253} 253}
254 254
255ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf, 255ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
@@ -328,19 +328,19 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
328 off += scnprintf(buf + off, buf_size - off, 328 off += scnprintf(buf + off, buf_size - off,
329 "\nNTB Incoming XLAT:\n"); 329 "\nNTB Incoming XLAT:\n");
330 330
331 u.v64 = ioread64(mmio + SKX_IMBAR1XBASE_OFFSET); 331 u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET);
332 off += scnprintf(buf + off, buf_size - off, 332 off += scnprintf(buf + off, buf_size - off,
333 "IMBAR1XBASE -\t\t%#018llx\n", u.v64); 333 "IMBAR1XBASE -\t\t%#018llx\n", u.v64);
334 334
335 u.v64 = ioread64(mmio + SKX_IMBAR2XBASE_OFFSET); 335 u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET);
336 off += scnprintf(buf + off, buf_size - off, 336 off += scnprintf(buf + off, buf_size - off,
337 "IMBAR2XBASE -\t\t%#018llx\n", u.v64); 337 "IMBAR2XBASE -\t\t%#018llx\n", u.v64);
338 338
339 u.v64 = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET); 339 u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
340 off += scnprintf(buf + off, buf_size - off, 340 off += scnprintf(buf + off, buf_size - off,
341 "IMBAR1XLMT -\t\t\t%#018llx\n", u.v64); 341 "IMBAR1XLMT -\t\t\t%#018llx\n", u.v64);
342 342
343 u.v64 = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET); 343 u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
344 off += scnprintf(buf + off, buf_size - off, 344 off += scnprintf(buf + off, buf_size - off,
345 "IMBAR2XLMT -\t\t\t%#018llx\n", u.v64); 345 "IMBAR2XLMT -\t\t\t%#018llx\n", u.v64);
346 346
@@ -348,34 +348,34 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
348 off += scnprintf(buf + off, buf_size - off, 348 off += scnprintf(buf + off, buf_size - off,
349 "\nNTB Outgoing B2B XLAT:\n"); 349 "\nNTB Outgoing B2B XLAT:\n");
350 350
351 u.v64 = ioread64(mmio + SKX_EMBAR1XBASE_OFFSET); 351 u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET);
352 off += scnprintf(buf + off, buf_size - off, 352 off += scnprintf(buf + off, buf_size - off,
353 "EMBAR1XBASE -\t\t%#018llx\n", u.v64); 353 "EMBAR1XBASE -\t\t%#018llx\n", u.v64);
354 354
355 u.v64 = ioread64(mmio + SKX_EMBAR2XBASE_OFFSET); 355 u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET);
356 off += scnprintf(buf + off, buf_size - off, 356 off += scnprintf(buf + off, buf_size - off,
357 "EMBAR2XBASE -\t\t%#018llx\n", u.v64); 357 "EMBAR2XBASE -\t\t%#018llx\n", u.v64);
358 358
359 u.v64 = ioread64(mmio + SKX_EMBAR1XLMT_OFFSET); 359 u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET);
360 off += scnprintf(buf + off, buf_size - off, 360 off += scnprintf(buf + off, buf_size - off,
361 "EMBAR1XLMT -\t\t%#018llx\n", u.v64); 361 "EMBAR1XLMT -\t\t%#018llx\n", u.v64);
362 362
363 u.v64 = ioread64(mmio + SKX_EMBAR2XLMT_OFFSET); 363 u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET);
364 off += scnprintf(buf + off, buf_size - off, 364 off += scnprintf(buf + off, buf_size - off,
365 "EMBAR2XLMT -\t\t%#018llx\n", u.v64); 365 "EMBAR2XLMT -\t\t%#018llx\n", u.v64);
366 366
367 off += scnprintf(buf + off, buf_size - off, 367 off += scnprintf(buf + off, buf_size - off,
368 "\nNTB Secondary BAR:\n"); 368 "\nNTB Secondary BAR:\n");
369 369
370 u.v64 = ioread64(mmio + SKX_EMBAR0_OFFSET); 370 u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET);
371 off += scnprintf(buf + off, buf_size - off, 371 off += scnprintf(buf + off, buf_size - off,
372 "EMBAR0 -\t\t%#018llx\n", u.v64); 372 "EMBAR0 -\t\t%#018llx\n", u.v64);
373 373
374 u.v64 = ioread64(mmio + SKX_EMBAR1_OFFSET); 374 u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET);
375 off += scnprintf(buf + off, buf_size - off, 375 off += scnprintf(buf + off, buf_size - off,
376 "EMBAR1 -\t\t%#018llx\n", u.v64); 376 "EMBAR1 -\t\t%#018llx\n", u.v64);
377 377
378 u.v64 = ioread64(mmio + SKX_EMBAR2_OFFSET); 378 u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET);
379 off += scnprintf(buf + off, buf_size - off, 379 off += scnprintf(buf + off, buf_size - off,
380 "EMBAR2 -\t\t%#018llx\n", u.v64); 380 "EMBAR2 -\t\t%#018llx\n", u.v64);
381 } 381 }
@@ -383,7 +383,7 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
383 off += scnprintf(buf + off, buf_size - off, 383 off += scnprintf(buf + off, buf_size - off,
384 "\nNTB Statistics:\n"); 384 "\nNTB Statistics:\n");
385 385
386 u.v16 = ioread16(mmio + SKX_USMEMMISS_OFFSET); 386 u.v16 = ioread16(mmio + GEN3_USMEMMISS_OFFSET);
387 off += scnprintf(buf + off, buf_size - off, 387 off += scnprintf(buf + off, buf_size - off,
388 "Upstream Memory Miss -\t%u\n", u.v16); 388 "Upstream Memory Miss -\t%u\n", u.v16);
389 389
@@ -391,22 +391,22 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
391 "\nNTB Hardware Errors:\n"); 391 "\nNTB Hardware Errors:\n");
392 392
393 if (!pci_read_config_word(ndev->ntb.pdev, 393 if (!pci_read_config_word(ndev->ntb.pdev,
394 SKX_DEVSTS_OFFSET, &u.v16)) 394 GEN3_DEVSTS_OFFSET, &u.v16))
395 off += scnprintf(buf + off, buf_size - off, 395 off += scnprintf(buf + off, buf_size - off,
396 "DEVSTS -\t\t%#06x\n", u.v16); 396 "DEVSTS -\t\t%#06x\n", u.v16);
397 397
398 if (!pci_read_config_word(ndev->ntb.pdev, 398 if (!pci_read_config_word(ndev->ntb.pdev,
399 SKX_LINK_STATUS_OFFSET, &u.v16)) 399 GEN3_LINK_STATUS_OFFSET, &u.v16))
400 off += scnprintf(buf + off, buf_size - off, 400 off += scnprintf(buf + off, buf_size - off,
401 "LNKSTS -\t\t%#06x\n", u.v16); 401 "LNKSTS -\t\t%#06x\n", u.v16);
402 402
403 if (!pci_read_config_dword(ndev->ntb.pdev, 403 if (!pci_read_config_dword(ndev->ntb.pdev,
404 SKX_UNCERRSTS_OFFSET, &u.v32)) 404 GEN3_UNCERRSTS_OFFSET, &u.v32))
405 off += scnprintf(buf + off, buf_size - off, 405 off += scnprintf(buf + off, buf_size - off,
406 "UNCERRSTS -\t\t%#06x\n", u.v32); 406 "UNCERRSTS -\t\t%#06x\n", u.v32);
407 407
408 if (!pci_read_config_dword(ndev->ntb.pdev, 408 if (!pci_read_config_dword(ndev->ntb.pdev,
409 SKX_CORERRSTS_OFFSET, &u.v32)) 409 GEN3_CORERRSTS_OFFSET, &u.v32))
410 off += scnprintf(buf + off, buf_size - off, 410 off += scnprintf(buf + off, buf_size - off,
411 "CORERRSTS -\t\t%#06x\n", u.v32); 411 "CORERRSTS -\t\t%#06x\n", u.v32);
412 412
@@ -510,7 +510,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
510 510
511 /* setup the EP */ 511 /* setup the EP */
512 limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000; 512 limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
513 base = ioread64(mmio + SKX_EMBAR1_OFFSET + (8 * idx)); 513 base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx));
514 base &= ~0xf; 514 base &= ~0xf;
515 515
516 if (limit_reg && size != mw_size) 516 if (limit_reg && size != mw_size)
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.h b/drivers/ntb/hw/intel/ntb_hw_gen3.h
index 09fd1d3e6b5b..75fb86ca27bb 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen3.h
+++ b/drivers/ntb/hw/intel/ntb_hw_gen3.h
@@ -47,64 +47,63 @@
47#include "ntb_hw_intel.h" 47#include "ntb_hw_intel.h"
48 48
49/* Intel Skylake Xeon hardware */ 49/* Intel Skylake Xeon hardware */
50#define SKX_IMBAR1SZ_OFFSET 0x00d0 50#define GEN3_IMBAR1SZ_OFFSET 0x00d0
51#define SKX_IMBAR2SZ_OFFSET 0x00d1 51#define GEN3_IMBAR2SZ_OFFSET 0x00d1
52#define SKX_EMBAR1SZ_OFFSET 0x00d2 52#define GEN3_EMBAR1SZ_OFFSET 0x00d2
53#define SKX_EMBAR2SZ_OFFSET 0x00d3 53#define GEN3_EMBAR2SZ_OFFSET 0x00d3
54#define SKX_DEVCTRL_OFFSET 0x0098 54#define GEN3_DEVCTRL_OFFSET 0x0098
55#define SKX_DEVSTS_OFFSET 0x009a 55#define GEN3_DEVSTS_OFFSET 0x009a
56#define SKX_UNCERRSTS_OFFSET 0x014c 56#define GEN3_UNCERRSTS_OFFSET 0x014c
57#define SKX_CORERRSTS_OFFSET 0x0158 57#define GEN3_CORERRSTS_OFFSET 0x0158
58#define SKX_LINK_STATUS_OFFSET 0x01a2 58#define GEN3_LINK_STATUS_OFFSET 0x01a2
59 59
60#define SKX_NTBCNTL_OFFSET 0x0000 60#define GEN3_NTBCNTL_OFFSET 0x0000
61#define SKX_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */ 61#define GEN3_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
62#define SKX_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */ 62#define GEN3_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
63#define SKX_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */ 63#define GEN3_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
64#define SKX_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */ 64#define GEN3_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
65#define SKX_IM_INT_STATUS_OFFSET 0x0040 65#define GEN3_IM_INT_STATUS_OFFSET 0x0040
66#define SKX_IM_INT_DISABLE_OFFSET 0x0048 66#define GEN3_IM_INT_DISABLE_OFFSET 0x0048
67#define SKX_IM_SPAD_OFFSET 0x0080 /* SPAD */ 67#define GEN3_IM_SPAD_OFFSET 0x0080 /* SPAD */
68#define SKX_USMEMMISS_OFFSET 0x0070 68#define GEN3_USMEMMISS_OFFSET 0x0070
69#define SKX_INTVEC_OFFSET 0x00d0 69#define GEN3_INTVEC_OFFSET 0x00d0
70#define SKX_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */ 70#define GEN3_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
71#define SKX_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */ 71#define GEN3_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
72#define SKX_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */ 72#define GEN3_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
73#define SKX_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */ 73#define GEN3_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
74#define SKX_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */ 74#define GEN3_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
75#define SKX_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */ 75#define GEN3_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
76#define SKX_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */ 76#define GEN3_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
77#define SKX_EM_INT_STATUS_OFFSET 0x4040 77#define GEN3_EM_INT_STATUS_OFFSET 0x4040
78#define SKX_EM_INT_DISABLE_OFFSET 0x4048 78#define GEN3_EM_INT_DISABLE_OFFSET 0x4048
79#define SKX_EM_SPAD_OFFSET 0x4080 /* remote SPAD */ 79#define GEN3_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
80#define SKX_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */ 80#define GEN3_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
81#define SKX_SPCICMD_OFFSET 0x4504 /* SPCICMD */ 81#define GEN3_SPCICMD_OFFSET 0x4504 /* SPCICMD */
82#define SKX_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */ 82#define GEN3_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
83#define SKX_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */ 83#define GEN3_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
84#define SKX_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */ 84#define GEN3_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
85 85
86#define SKX_DB_COUNT 32 86#define GEN3_DB_COUNT 32
87#define SKX_DB_LINK 32 87#define GEN3_DB_LINK 32
88#define SKX_DB_LINK_BIT BIT_ULL(SKX_DB_LINK) 88#define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK)
89#define SKX_DB_MSIX_VECTOR_COUNT 33 89#define GEN3_DB_MSIX_VECTOR_COUNT 33
90#define SKX_DB_MSIX_VECTOR_SHIFT 1 90#define GEN3_DB_MSIX_VECTOR_SHIFT 1
91#define SKX_DB_TOTAL_SHIFT 33 91#define GEN3_DB_TOTAL_SHIFT 33
92#define SKX_SPAD_COUNT 16 92#define GEN3_SPAD_COUNT 16
93 93
94static inline u64 skx_db_ioread(void __iomem *mmio) 94static inline u64 gen3_db_ioread(void __iomem *mmio)
95{ 95{
96 return ioread64(mmio); 96 return ioread64(mmio);
97} 97}
98 98
99static inline void skx_db_iowrite(u64 bits, void __iomem *mmio) 99static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
100{ 100{
101 iowrite64(bits, mmio); 101 iowrite64(bits, mmio);
102} 102}
103 103
104ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf, 104ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
105 size_t count, loff_t *offp); 105 size_t count, loff_t *offp);
106int skx_init_dev(struct intel_ntb_dev *ndev); 106int gen3_init_dev(struct intel_ntb_dev *ndev);
107int skx_poll_link(struct intel_ntb_dev *ndev);
108 107
109extern const struct ntb_dev_ops intel_ntb3_ops; 108extern const struct ntb_dev_ops intel_ntb3_ops;
110 109
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index 46d757c3850e..c49ff8970ce3 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -187,7 +187,7 @@ struct intel_ntb_dev {
187#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \ 187#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
188 hb_timer.work) 188 hb_timer.work)
189 189
190static inline int pdev_is_xeon(struct pci_dev *pdev) 190static inline int pdev_is_gen1(struct pci_dev *pdev)
191{ 191{
192 switch (pdev->device) { 192 switch (pdev->device) {
193 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: 193 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
@@ -210,7 +210,7 @@ static inline int pdev_is_xeon(struct pci_dev *pdev)
210 return 0; 210 return 0;
211} 211}
212 212
213static inline int pdev_is_skx_xeon(struct pci_dev *pdev) 213static inline int pdev_is_gen3(struct pci_dev *pdev)
214{ 214{
215 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX) 215 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
216 return 1; 216 return 1;
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-11 16:42:51 -0400