diff options
author | Christian König <christian.koenig@amd.com> | 2018-01-19 08:17:40 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:18:20 -0500 |
commit | 698825653fdf1a696e1b9458ed9fc4aa2c6587d4 (patch) | |
tree | 4ddb3d0444c4c0ae531dfff131e40ad8c2b02768 /drivers | |
parent | 3c9d1fde7f63b6f7f30e9a5366fbc2fe249e0b74 (diff) |
drm/amdgpu: add optional ring to *_hdp callbacks
This adds an optional ring to the invalidate_hdp and flush_hdp
callbacks. If the ring isn't specified or the emit_wreg function not
available the HDP operation will be done with the CPU otherwise by
writing on the ring.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik.c | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/si.c | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vi.c | 21 |
10 files changed, 81 insertions, 36 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 93ab458e272e..8367f92de09a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -1221,9 +1221,10 @@ struct amdgpu_asic_funcs { | |||
1221 | /* get config memsize register */ | 1221 | /* get config memsize register */ |
1222 | u32 (*get_config_memsize)(struct amdgpu_device *adev); | 1222 | u32 (*get_config_memsize)(struct amdgpu_device *adev); |
1223 | /* flush hdp write queue */ | 1223 | /* flush hdp write queue */ |
1224 | void (*flush_hdp)(struct amdgpu_device *adev); | 1224 | void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
1225 | /* invalidate hdp read cache */ | 1225 | /* invalidate hdp read cache */ |
1226 | void (*invalidate_hdp)(struct amdgpu_device *adev); | 1226 | void (*invalidate_hdp)(struct amdgpu_device *adev, |
1227 | struct amdgpu_ring *ring); | ||
1227 | }; | 1228 | }; |
1228 | 1229 | ||
1229 | /* | 1230 | /* |
@@ -1367,7 +1368,7 @@ struct amdgpu_nbio_funcs { | |||
1367 | u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); | 1368 | u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); |
1368 | u32 (*get_rev_id)(struct amdgpu_device *adev); | 1369 | u32 (*get_rev_id)(struct amdgpu_device *adev); |
1369 | void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); | 1370 | void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); |
1370 | void (*hdp_flush)(struct amdgpu_device *adev); | 1371 | void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
1371 | u32 (*get_memsize)(struct amdgpu_device *adev); | 1372 | u32 (*get_memsize)(struct amdgpu_device *adev); |
1372 | void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, | 1373 | void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, |
1373 | bool use_doorbell, int doorbell_index); | 1374 | bool use_doorbell, int doorbell_index); |
@@ -1774,8 +1775,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |||
1774 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) | 1775 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
1775 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) | 1776 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
1776 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) | 1777 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) |
1777 | #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev)) | 1778 | #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) |
1778 | #define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev)) | 1779 | #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) |
1779 | #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) | 1780 | #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) |
1780 | #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr)) | 1781 | #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr)) |
1781 | #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | 1782 | #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 18d23878ad14..56b0b305a9fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | |||
@@ -247,7 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, | |||
247 | } | 247 | } |
248 | } | 248 | } |
249 | mb(); | 249 | mb(); |
250 | amdgpu_asic_flush_hdp(adev); | 250 | amdgpu_asic_flush_hdp(adev, NULL); |
251 | amdgpu_gmc_flush_gpu_tlb(adev, 0); | 251 | amdgpu_gmc_flush_gpu_tlb(adev, 0); |
252 | return 0; | 252 | return 0; |
253 | } | 253 | } |
@@ -330,7 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, | |||
330 | return r; | 330 | return r; |
331 | 331 | ||
332 | mb(); | 332 | mb(); |
333 | amdgpu_asic_flush_hdp(adev); | 333 | amdgpu_asic_flush_hdp(adev, NULL); |
334 | amdgpu_gmc_flush_gpu_tlb(adev, 0); | 334 | amdgpu_gmc_flush_gpu_tlb(adev, 0); |
335 | return 0; | 335 | return 0; |
336 | } | 336 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 2dca47ad4f09..0df52cb1765b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |||
@@ -854,7 +854,7 @@ restart: | |||
854 | if (vm->use_cpu_for_update) { | 854 | if (vm->use_cpu_for_update) { |
855 | /* Flush HDP */ | 855 | /* Flush HDP */ |
856 | mb(); | 856 | mb(); |
857 | amdgpu_asic_flush_hdp(adev); | 857 | amdgpu_asic_flush_hdp(adev, NULL); |
858 | } else if (params.ib->length_dw == 0) { | 858 | } else if (params.ib->length_dw == 0) { |
859 | amdgpu_job_free(job); | 859 | amdgpu_job_free(job); |
860 | } else { | 860 | } else { |
@@ -1436,7 +1436,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |||
1436 | if (vm->use_cpu_for_update) { | 1436 | if (vm->use_cpu_for_update) { |
1437 | /* Flush HDP */ | 1437 | /* Flush HDP */ |
1438 | mb(); | 1438 | mb(); |
1439 | amdgpu_asic_flush_hdp(adev); | 1439 | amdgpu_asic_flush_hdp(adev, NULL); |
1440 | } | 1440 | } |
1441 | 1441 | ||
1442 | spin_lock(&vm->status_lock); | 1442 | spin_lock(&vm->status_lock); |
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 204ce807372c..4324184996a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c | |||
@@ -1715,16 +1715,25 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev) | |||
1715 | adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; | 1715 | adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; |
1716 | } | 1716 | } |
1717 | 1717 | ||
1718 | static void cik_flush_hdp(struct amdgpu_device *adev) | 1718 | static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
1719 | { | 1719 | { |
1720 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); | 1720 | if (!ring || !ring->funcs->emit_wreg) { |
1721 | RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); | 1721 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); |
1722 | RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); | ||
1723 | } else { | ||
1724 | amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); | ||
1725 | } | ||
1722 | } | 1726 | } |
1723 | 1727 | ||
1724 | static void cik_invalidate_hdp(struct amdgpu_device *adev) | 1728 | static void cik_invalidate_hdp(struct amdgpu_device *adev, |
1729 | struct amdgpu_ring *ring) | ||
1725 | { | 1730 | { |
1726 | WREG32(mmHDP_DEBUG0, 1); | 1731 | if (!ring || !ring->funcs->emit_wreg) { |
1727 | RREG32(mmHDP_DEBUG0); | 1732 | WREG32(mmHDP_DEBUG0, 1); |
1733 | RREG32(mmHDP_DEBUG0); | ||
1734 | } else { | ||
1735 | amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); | ||
1736 | } | ||
1728 | } | 1737 | } |
1729 | 1738 | ||
1730 | static const struct amdgpu_asic_funcs cik_asic_funcs = | 1739 | static const struct amdgpu_asic_funcs cik_asic_funcs = |
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e90eaafabeb1..4a82526652cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | |||
@@ -1009,7 +1009,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) | |||
1009 | WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); | 1009 | WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); |
1010 | 1010 | ||
1011 | /* After HDP is initialized, flush HDP.*/ | 1011 | /* After HDP is initialized, flush HDP.*/ |
1012 | adev->nbio_funcs->hdp_flush(adev); | 1012 | adev->nbio_funcs->hdp_flush(adev, NULL); |
1013 | 1013 | ||
1014 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) | 1014 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
1015 | value = false; | 1015 | value = false; |
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index d4da663d5eb0..2daeef6e9345 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | |||
@@ -53,9 +53,16 @@ static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) | |||
53 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); | 53 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); |
54 | } | 54 | } |
55 | 55 | ||
56 | static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) | 56 | static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev, |
57 | struct amdgpu_ring *ring) | ||
57 | { | 58 | { |
58 | WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); | 59 | if (!ring || !ring->funcs->emit_wreg) |
60 | WREG32_SOC15_NO_KIQ(NBIO, 0, | ||
61 | mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, | ||
62 | 0); | ||
63 | else | ||
64 | amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( | ||
65 | NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); | ||
59 | } | 66 | } |
60 | 67 | ||
61 | static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) | 68 | static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) |
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 17a9131a4598..cd10c76a76e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | |||
@@ -53,9 +53,14 @@ static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) | |||
53 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); | 53 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); |
54 | } | 54 | } |
55 | 55 | ||
56 | static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev) | 56 | static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev, |
57 | struct amdgpu_ring *ring) | ||
57 | { | 58 | { |
58 | WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); | 59 | if (!ring || !ring->funcs->emit_wreg) |
60 | WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); | ||
61 | else | ||
62 | amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( | ||
63 | NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0); | ||
59 | } | 64 | } |
60 | 65 | ||
61 | static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) | 66 | static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) |
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index f61a431b9553..f20c4b7414e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c | |||
@@ -1230,16 +1230,25 @@ static void si_detect_hw_virtualization(struct amdgpu_device *adev) | |||
1230 | adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; | 1230 | adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; |
1231 | } | 1231 | } |
1232 | 1232 | ||
1233 | static void si_flush_hdp(struct amdgpu_device *adev) | 1233 | static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
1234 | { | 1234 | { |
1235 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); | 1235 | if (!ring || !ring->funcs->emit_wreg) { |
1236 | RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); | 1236 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); |
1237 | RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); | ||
1238 | } else { | ||
1239 | amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); | ||
1240 | } | ||
1237 | } | 1241 | } |
1238 | 1242 | ||
1239 | static void si_invalidate_hdp(struct amdgpu_device *adev) | 1243 | static void si_invalidate_hdp(struct amdgpu_device *adev, |
1244 | struct amdgpu_ring *ring) | ||
1240 | { | 1245 | { |
1241 | WREG32(mmHDP_DEBUG0, 1); | 1246 | if (!ring || !ring->funcs->emit_wreg) { |
1242 | RREG32(mmHDP_DEBUG0); | 1247 | WREG32(mmHDP_DEBUG0, 1); |
1248 | RREG32(mmHDP_DEBUG0); | ||
1249 | } else { | ||
1250 | amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); | ||
1251 | } | ||
1243 | } | 1252 | } |
1244 | 1253 | ||
1245 | static const struct amdgpu_asic_funcs si_asic_funcs = | 1254 | static const struct amdgpu_asic_funcs si_asic_funcs = |
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index ad39ffd012bc..04a471b80064 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c | |||
@@ -583,14 +583,19 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) | |||
583 | return adev->nbio_funcs->get_rev_id(adev); | 583 | return adev->nbio_funcs->get_rev_id(adev); |
584 | } | 584 | } |
585 | 585 | ||
586 | static void soc15_flush_hdp(struct amdgpu_device *adev) | 586 | static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
587 | { | 587 | { |
588 | adev->nbio_funcs->hdp_flush(adev); | 588 | adev->nbio_funcs->hdp_flush(adev, ring); |
589 | } | 589 | } |
590 | 590 | ||
591 | static void soc15_invalidate_hdp(struct amdgpu_device *adev) | 591 | static void soc15_invalidate_hdp(struct amdgpu_device *adev, |
592 | struct amdgpu_ring *ring) | ||
592 | { | 593 | { |
593 | WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); | 594 | if (!ring || !ring->funcs->emit_wreg) |
595 | WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); | ||
596 | else | ||
597 | amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( | ||
598 | HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); | ||
594 | } | 599 | } |
595 | 600 | ||
596 | static const struct amdgpu_asic_funcs soc15_asic_funcs = | 601 | static const struct amdgpu_asic_funcs soc15_asic_funcs = |
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index fbb77b959f8a..61360a1552d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c | |||
@@ -856,16 +856,25 @@ static uint32_t vi_get_rev_id(struct amdgpu_device *adev) | |||
856 | >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; | 856 | >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; |
857 | } | 857 | } |
858 | 858 | ||
859 | static void vi_flush_hdp(struct amdgpu_device *adev) | 859 | static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
860 | { | 860 | { |
861 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); | 861 | if (!ring || !ring->funcs->emit_wreg) { |
862 | RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); | 862 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); |
863 | RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); | ||
864 | } else { | ||
865 | amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); | ||
866 | } | ||
863 | } | 867 | } |
864 | 868 | ||
865 | static void vi_invalidate_hdp(struct amdgpu_device *adev) | 869 | static void vi_invalidate_hdp(struct amdgpu_device *adev, |
870 | struct amdgpu_ring *ring) | ||
866 | { | 871 | { |
867 | WREG32(mmHDP_DEBUG0, 1); | 872 | if (!ring || !ring->funcs->emit_wreg) { |
868 | RREG32(mmHDP_DEBUG0); | 873 | WREG32(mmHDP_DEBUG0, 1); |
874 | RREG32(mmHDP_DEBUG0); | ||
875 | } else { | ||
876 | amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); | ||
877 | } | ||
869 | } | 878 | } |
870 | 879 | ||
871 | static const struct amdgpu_asic_funcs vi_asic_funcs = | 880 | static const struct amdgpu_asic_funcs vi_asic_funcs = |