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authorGertjan van Wingerde <gwingerde@gmail.com>2010-04-11 08:31:14 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-12 15:22:13 -0400
commit64522957ce35df995dfd73bee548304f2a39cc3e (patch)
treefa074f5b2de6ba34c5db557ee2fca4ebe74c5443 /drivers
parentd5385bfc59c737d1eae77cc48d662daf4ddddae8 (diff)
rt2x00: Add rt3090 support in rt2800 register initialization.
Add RT3090 specific register initializations to rt2x00, based on the latest Ralink rt3090 vendor driver. Untested as I don't actually own an RT3090 based device, but given experiences on rt3070/rt3071 very hopeful that this will actually work.. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c54
1 files changed, 40 insertions, 14 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index fe7171f408ba..d74608228a99 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -1043,7 +1043,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1043{ 1043{
1044 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1044 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1045 if (rt2x00_rt(rt2x00dev, RT3070) || 1045 if (rt2x00_rt(rt2x00dev, RT3070) ||
1046 rt2x00_rt(rt2x00dev, RT3071)) 1046 rt2x00_rt(rt2x00dev, RT3071) ||
1047 rt2x00_rt(rt2x00dev, RT3090))
1047 return 0x1c + (2 * rt2x00dev->lna_gain); 1048 return 0x1c + (2 * rt2x00dev->lna_gain);
1048 else 1049 else
1049 return 0x2e + rt2x00dev->lna_gain; 1050 return 0x2e + rt2x00dev->lna_gain;
@@ -1192,10 +1193,12 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1192 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 1193 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1193 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1194 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1194 1195
1195 if (rt2x00_rt(rt2x00dev, RT3071)) { 1196 if (rt2x00_rt(rt2x00dev, RT3071) ||
1197 rt2x00_rt(rt2x00dev, RT3090)) {
1196 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1198 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1197 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1199 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1198 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) { 1200 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1201 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1199 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1202 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1200 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST)) 1203 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1201 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 1204 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
@@ -1558,7 +1561,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1558 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1561 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1559 1562
1560 if (rt2x00_rt(rt2x00dev, RT3070) || 1563 if (rt2x00_rt(rt2x00dev, RT3070) ||
1561 rt2x00_rt(rt2x00dev, RT3071)) { 1564 rt2x00_rt(rt2x00dev, RT3071) ||
1565 rt2x00_rt(rt2x00dev, RT3090)) {
1562 rt2800_bbp_write(rt2x00dev, 79, 0x13); 1566 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1563 rt2800_bbp_write(rt2x00dev, 80, 0x05); 1567 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1564 rt2800_bbp_write(rt2x00dev, 81, 0x33); 1568 rt2800_bbp_write(rt2x00dev, 81, 0x33);
@@ -1580,7 +1584,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1580 rt2800_bbp_write(rt2x00dev, 92, 0x00); 1584 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1581 1585
1582 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 1586 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1583 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E)) 1587 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1588 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
1584 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 1589 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1585 else 1590 else
1586 rt2800_bbp_write(rt2x00dev, 103, 0x00); 1591 rt2800_bbp_write(rt2x00dev, 103, 0x00);
@@ -1588,7 +1593,8 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1588 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1593 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1589 rt2800_bbp_write(rt2x00dev, 106, 0x35); 1594 rt2800_bbp_write(rt2x00dev, 106, 0x35);
1590 1595
1591 if (rt2x00_rt(rt2x00dev, RT3071)) { 1596 if (rt2x00_rt(rt2x00dev, RT3071) ||
1597 rt2x00_rt(rt2x00dev, RT3090)) {
1592 rt2800_bbp_read(rt2x00dev, 138, &value); 1598 rt2800_bbp_read(rt2x00dev, 138, &value);
1593 1599
1594 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 1600 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
@@ -1688,7 +1694,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1688 u16 eeprom; 1694 u16 eeprom;
1689 1695
1690 if (!rt2x00_rt(rt2x00dev, RT3070) && 1696 if (!rt2x00_rt(rt2x00dev, RT3070) &&
1691 !rt2x00_rt(rt2x00dev, RT3071)) 1697 !rt2x00_rt(rt2x00dev, RT3071) &&
1698 !rt2x00_rt(rt2x00dev, RT3090))
1692 return 0; 1699 return 0;
1693 1700
1694 /* 1701 /*
@@ -1702,7 +1709,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1702 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1709 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1703 1710
1704 if (rt2x00_rt(rt2x00dev, RT3070) || 1711 if (rt2x00_rt(rt2x00dev, RT3070) ||
1705 rt2x00_rt(rt2x00dev, RT3071)) { 1712 rt2x00_rt(rt2x00dev, RT3071) ||
1713 rt2x00_rt(rt2x00dev, RT3090)) {
1706 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1714 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1707 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1715 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1708 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1716 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
@@ -1729,7 +1737,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1729 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); 1737 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1730 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); 1738 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1731 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 1739 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1732 } else if (rt2x00_rt(rt2x00dev, RT3071)) { 1740 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1741 rt2x00_rt(rt2x00dev, RT3090)) {
1733 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 1742 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1734 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 1743 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1735 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 1744 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
@@ -1738,7 +1747,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1738 1747
1739 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); 1748 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1740 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); 1749 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1741 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) { 1750 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1751 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1742 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1752 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1743 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST)) 1753 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1744 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); 1754 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
@@ -1756,7 +1766,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1756 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); 1766 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1757 rt2x00dev->calibration[1] = 1767 rt2x00dev->calibration[1] =
1758 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 1768 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1759 } else if (rt2x00_rt(rt2x00dev, RT3071)) { 1769 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1770 rt2x00_rt(rt2x00dev, RT3090)) {
1760 rt2x00dev->calibration[0] = 1771 rt2x00dev->calibration[0] =
1761 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); 1772 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1762 rt2x00dev->calibration[1] = 1773 rt2x00dev->calibration[1] =
@@ -1780,7 +1791,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1780 rt2800_bbp_write(rt2x00dev, 4, bbp); 1791 rt2800_bbp_write(rt2x00dev, 4, bbp);
1781 1792
1782 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 1793 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1783 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) 1794 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1795 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
1784 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 1796 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1785 1797
1786 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg); 1798 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
@@ -1789,7 +1801,8 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1789 1801
1790 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 1802 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1791 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 1803 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1792 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E)) { 1804 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1805 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1793 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1806 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1794 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 1807 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1795 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 1808 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
@@ -1801,7 +1814,20 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1801 EEPROM_TXMIXER_GAIN_BG_VAL)); 1814 EEPROM_TXMIXER_GAIN_BG_VAL));
1802 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 1815 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1803 1816
1804 if (rt2x00_rt(rt2x00dev, RT3071)) { 1817 if (rt2x00_rt(rt2x00dev, RT3090)) {
1818 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1819
1820 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1821 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1822 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1823 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1824 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1825
1826 rt2800_bbp_write(rt2x00dev, 138, bbp);
1827 }
1828
1829 if (rt2x00_rt(rt2x00dev, RT3071) ||
1830 rt2x00_rt(rt2x00dev, RT3090)) {
1805 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 1831 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1806 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 1832 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1807 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 1833 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);