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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-10-08 04:43:34 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-10-19 11:56:02 -0400
commit606bb5e0b28b540685fb94c22902cd9a948a3779 (patch)
tree8321a7197eec77ba9f55c8acb7c180235ca850e4 /drivers
parentc562657a75282afb00498ea82949ba7a9944ed15 (diff)
drm/i915: Use round to closest when computing the CEA 1.001 pixel clocks
drm_edid.c now computes the alternate CEA clocks using DIV_ROUND_CLOSEST(), so follow suit in the N/CTS setup to make sure we pick the right setting for the mode. Unfortunately we can't actually use DIV_ROUND_CLOSEST() here due to the ({}) construct used, so just stick in raw numbers instead. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Libin Yang <libin.yang@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_audio.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 56c2f54801c4..4dccd9b003a1 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -61,21 +61,21 @@ static const struct {
61 int clock; 61 int clock;
62 u32 config; 62 u32 config;
63} hdmi_audio_clock[] = { 63} hdmi_audio_clock[] = {
64 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
67 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
69 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
70 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
72 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
74}; 74};
75 75
76/* HDMI N/CTS table */ 76/* HDMI N/CTS table */
77#define TMDS_297M 297000 77#define TMDS_297M 297000
78#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001) 78#define TMDS_296M 296703
79static const struct { 79static const struct {
80 int sample_rate; 80 int sample_rate;
81 int clock; 81 int clock;