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authorJan Kotas <jank@cadence.com>2018-12-13 07:49:29 -0500
committerStephen Boyd <sboyd@kernel.org>2019-01-09 14:41:19 -0500
commit50cc4caf531abb2075c6973451fccdaba9f02715 (patch)
treea7b2868a62a7d3166bbd607ed4d8cdc3b80cb73e /drivers
parent5b42aac8904bfe8fcd65179c0fe71a6a1109ee53 (diff)
clk: Add Fixed MMIO clock driver
This patch adds a driver for Fixed MMIO clock. The driver reads a clock frequency value from a single 32-bit memory mapped register and registers it as a fixed rate clock. It can be enabled with COMMON_CLK_FIXED_MMIO Kconfig option. Signed-off-by: Jan Kotas <jank@cadence.com> [sboyd@kernel.org: Make of_fixed_mmio_clk_setup() static, use clk_hw based APIs] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/Kconfig6
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-fixed-mmio.c101
3 files changed, 108 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index e5b2fe80eab4..296972518db4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -290,6 +290,12 @@ config COMMON_CLK_BD718XX
290 This driver supports ROHM BD71837 and ROHM BD71847 290 This driver supports ROHM BD71837 and ROHM BD71847
291 PMICs clock gates. 291 PMICs clock gates.
292 292
293config COMMON_CLK_FIXED_MMIO
294 bool "Clock driver for Memory Mapped Fixed values"
295 depends on COMMON_CLK && OF
296 help
297 Support for Memory Mapped IO Fixed clocks
298
293source "drivers/clk/actions/Kconfig" 299source "drivers/clk/actions/Kconfig"
294source "drivers/clk/bcm/Kconfig" 300source "drivers/clk/bcm/Kconfig"
295source "drivers/clk/hisilicon/Kconfig" 301source "drivers/clk/hisilicon/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8a9440a97500..d6cd32bda771 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
27obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o 27obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
28obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o 28obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
29obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 29obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
30obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o 31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
31obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o 32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
32obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 33obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
diff --git a/drivers/clk/clk-fixed-mmio.c b/drivers/clk/clk-fixed-mmio.c
new file mode 100644
index 000000000000..d1a97d971183
--- /dev/null
+++ b/drivers/clk/clk-fixed-mmio.c
@@ -0,0 +1,101 @@
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Memory Mapped IO Fixed clock driver
5 *
6 * Copyright (C) 2018 Cadence Design Systems, Inc.
7 *
8 * Authors:
9 * Jan Kotas <jank@cadence.com>
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/of_address.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16
17static struct clk_hw *fixed_mmio_clk_setup(struct device_node *node)
18{
19 struct clk_hw *clk;
20 const char *clk_name = node->name;
21 void __iomem *base;
22 u32 freq;
23 int ret;
24
25 base = of_iomap(node, 0);
26 if (!base) {
27 pr_err("%pOFn: failed to map address\n", node);
28 return ERR_PTR(-EIO);
29 }
30
31 freq = readl(base);
32 iounmap(base);
33 of_property_read_string(node, "clock-output-names", &clk_name);
34
35 clk = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, freq);
36 if (IS_ERR(clk)) {
37 pr_err("%pOFn: failed to register fixed rate clock\n", node);
38 return clk;
39 }
40
41 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, clk);
42 if (ret) {
43 pr_err("%pOFn: failed to add clock provider\n", node);
44 clk_hw_unregister(clk);
45 clk = ERR_PTR(ret);
46 }
47
48 return clk;
49}
50
51static void __init of_fixed_mmio_clk_setup(struct device_node *node)
52{
53 fixed_mmio_clk_setup(node);
54}
55CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
56
57/**
58 * This is not executed when of_fixed_mmio_clk_setup succeeded.
59 */
60static int of_fixed_mmio_clk_probe(struct platform_device *pdev)
61{
62 struct clk_hw *clk;
63
64 clk = fixed_mmio_clk_setup(pdev->dev.of_node);
65 if (IS_ERR(clk))
66 return PTR_ERR(clk);
67
68 platform_set_drvdata(pdev, clk);
69
70 return 0;
71}
72
73static int of_fixed_mmio_clk_remove(struct platform_device *pdev)
74{
75 struct clk_hw *clk = platform_get_drvdata(pdev);
76
77 of_clk_del_provider(pdev->dev.of_node);
78 clk_hw_unregister_fixed_rate(clk);
79
80 return 0;
81}
82
83static const struct of_device_id of_fixed_mmio_clk_ids[] = {
84 { .compatible = "fixed-mmio-clock" },
85 { }
86};
87MODULE_DEVICE_TABLE(of, of_fixed_mmio_clk_ids);
88
89static struct platform_driver of_fixed_mmio_clk_driver = {
90 .driver = {
91 .name = "of_fixed_mmio_clk",
92 .of_match_table = of_fixed_mmio_clk_ids,
93 },
94 .probe = of_fixed_mmio_clk_probe,
95 .remove = of_fixed_mmio_clk_remove,
96};
97module_platform_driver(of_fixed_mmio_clk_driver);
98
99MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
100MODULE_DESCRIPTION("Memory Mapped IO Fixed clock driver");
101MODULE_LICENSE("GPL v2");