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authorLinus Torvalds <torvalds@linux-foundation.org>2016-12-01 19:44:42 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2016-12-01 19:44:42 -0500
commit4db5e636ddca41f4292359fdb3ac7cc4346a359a (patch)
tree7cad70c84b3a7a79dce4f77ec7f51ec4621d7f56 /drivers
parent2caceb3294a78c389b462e7e236a4e744a53a474 (diff)
parente42010d8207f9d15a605ceb8e321bcd9648071b0 (diff)
Merge tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas: "PCI fixes: - Fix Read Completion Boundary setting, which fixes a boot failure on IBM x3850 with Mellanox MT27500 ConnectX-3 - Update some MAINTAINERS entries and email addresses" * tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX) PCI: Export pcie_find_root_port PCI: designware-plat: Update author email PCI: designware: Change maintainer to Joao Pinto MAINTAINERS: Add devicetree binding to PCI i.MX6 entry MAINTAINERS: Update Richard Zhu's email address
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/host/pcie-designware-plat.c2
-rw-r--r--drivers/pci/pcie/aer/aer_inject.c14
-rw-r--r--drivers/pci/probe.c28
3 files changed, 28 insertions, 16 deletions
diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c
index 8df6312ed300..1a02038c4640 100644
--- a/drivers/pci/host/pcie-designware-plat.c
+++ b/drivers/pci/host/pcie-designware-plat.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 4 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
5 * 5 *
6 * Authors: Joao Pinto <jpmpinto@gmail.com> 6 * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index db553dc22c8e..2b6a59266689 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -307,20 +307,6 @@ out:
307 return 0; 307 return 0;
308} 308}
309 309
310static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
311{
312 while (1) {
313 if (!pci_is_pcie(dev))
314 break;
315 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
316 return dev;
317 if (!dev->bus->self)
318 break;
319 dev = dev->bus->self;
320 }
321 return NULL;
322}
323
324static int find_aer_device_iter(struct device *device, void *data) 310static int find_aer_device_iter(struct device *device, void *data)
325{ 311{
326 struct pcie_device **result = data; 312 struct pcie_device **result = data;
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ab002671fa60..104c46d53121 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1439,6 +1439,21 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1439 dev_warn(&dev->dev, "PCI-X settings not supported\n"); 1439 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1440} 1440}
1441 1441
1442static bool pcie_root_rcb_set(struct pci_dev *dev)
1443{
1444 struct pci_dev *rp = pcie_find_root_port(dev);
1445 u16 lnkctl;
1446
1447 if (!rp)
1448 return false;
1449
1450 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1451 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1452 return true;
1453
1454 return false;
1455}
1456
1442static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) 1457static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1443{ 1458{
1444 int pos; 1459 int pos;
@@ -1468,9 +1483,20 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1468 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); 1483 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1469 1484
1470 /* Initialize Link Control Register */ 1485 /* Initialize Link Control Register */
1471 if (pcie_cap_has_lnkctl(dev)) 1486 if (pcie_cap_has_lnkctl(dev)) {
1487
1488 /*
1489 * If the Root Port supports Read Completion Boundary of
1490 * 128, set RCB to 128. Otherwise, clear it.
1491 */
1492 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1493 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1494 if (pcie_root_rcb_set(dev))
1495 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1496
1472 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, 1497 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1473 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); 1498 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1499 }
1474 1500
1475 /* Find Advanced Error Reporting Enhanced Capability */ 1501 /* Find Advanced Error Reporting Enhanced Capability */
1476 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 1502 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);