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authorWei Yongjun <weiyongjun1@huawei.com>2017-04-25 10:36:42 -0400
committerBen Skeggs <bskeggs@redhat.com>2017-04-29 08:39:23 -0400
commit48907c23ea3307a6b6368698c1e786152cd45588 (patch)
tree209476fb0b91723390b6edb2f63bfe23d3a2b40a /drivers
parent60b95d709525e3ce1c51e1fc93175dcd1755d345 (diff)
drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr()
The error return code PTR_ERR(mc) is always 0 since mc is equal to 0 in this error handling case. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
index b10ed59a4911..30491d132d59 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
@@ -48,7 +48,7 @@ gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
48 mc = ioremap(mc_base, 0xd00); 48 mc = ioremap(mc_base, 0xd00);
49 if (!mc) { 49 if (!mc) {
50 nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); 50 nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
51 return PTR_ERR(mc); 51 return -ENOMEM;
52 } 52 }
53 sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | 53 sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
54 ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); 54 ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);