drm/amdgpu/gfx: create a common bitmask function (v2)

The same function was duplicated in all the gfx IPs. Use
a single implementation for all.

v2: use static inline (Alex Xie)

Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
Suggested-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5 files changed, 25 insertions, 40 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index e02044086445..2d846ef1c033 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -30,4 +30,17 @@ void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
                 unsigned max_sh);
 
+/**
+ * amdgpu_gfx_create_bitmask - create a bitmask
+ *
+ * @bit_width: length of the mask
+ *
+ * create a variable length bit mask.
+ * Returns the bitmask.
+ */
+static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
+{
+        return (u32)((1ULL << bit_width) - 1);
+}
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index c2b4e9fbc616..7b0b3cf16334 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1114,11 +1114,6 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
         WREG32(mmGRBM_GFX_INDEX, data);
 }
 
-static u32 gfx_v6_0_create_bitmask(u32 bit_width)
-{
-        return (u32)(((u64)1 << bit_width) - 1);
-}
-
 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 {
         u32 data, mask;
@@ -1128,8 +1123,8 @@ static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 
         data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
 
-        mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_backends_per_se/
-                                        adev->gfx.config.max_sh_per_se);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
+                                         adev->gfx.config.max_sh_per_se);
 
         return ~data & mask;
 }
@@ -1331,7 +1326,7 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
                 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
 
-        mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
         return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index ae9861134f8b..4c04e9dec28b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1608,19 +1608,6 @@ static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
 }
 
 /**
- * gfx_v7_0_create_bitmask - create a bitmask
- *
- * @bit_width: length of the mask
- *
- * create a variable length bit mask (CIK).
- * Returns the bitmask.
- */
-static u32 gfx_v7_0_create_bitmask(u32 bit_width)
-{
-        return (u32)((1ULL << bit_width) - 1);
-}
-
-/**
  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
  *
  * @adev: amdgpu_device pointer
@@ -1638,8 +1625,8 @@ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
 
-        mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-                                       adev->gfx.config.max_sh_per_se);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
+                                         adev->gfx.config.max_sh_per_se);
 
         return (~data) & mask;
 }
@@ -4157,7 +4144,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
 
-        mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
 
         return (~data) & mask;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index afd7d6518aaa..ad2e0bba5c93 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3635,11 +3635,6 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
         WREG32(mmGRBM_GFX_INDEX, data);
 }
 
-static u32 gfx_v8_0_create_bitmask(u32 bit_width)
-{
-        return (u32)((1ULL << bit_width) - 1);
-}
-
 static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 {
         u32 data, mask;
@@ -3649,8 +3644,8 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 
         data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
 
-        mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-                                       adev->gfx.config.max_sh_per_se);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
+                                         adev->gfx.config.max_sh_per_se);
 
         return (~data) & mask;
 }
@@ -7150,7 +7145,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
         data =  RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
                 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
 
-        mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
 
         return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 276dc06345af..cf15a350d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1698,11 +1698,6 @@ static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh
         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 }
 
-static u32 gfx_v9_0_create_bitmask(u32 bit_width)
-{
-        return (u32)((1ULL << bit_width) - 1);
-}
-
 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 {
         u32 data, mask;
@@ -1713,8 +1708,8 @@ static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
 
-        mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
-                                       adev->gfx.config.max_sh_per_se);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
+                                         adev->gfx.config.max_sh_per_se);
 
         return (~data) & mask;
 }
@@ -4609,7 +4604,7 @@ static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
 
-        mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
+        mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
 
         return (~data) & mask;
 }