diff options
author | Harry Wentland <harry.wentland@amd.com> | 2017-09-05 15:50:48 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:17:36 -0400 |
commit | 21e67d4d52ca8688feb8c4f6e6d29b2d16d578ad (patch) | |
tree | 443a216be2ae1d2374bafd03b4612001e20f234e /drivers | |
parent | e74c6972f85d48de4d2fe797ddd0fbc8bd899f0e (diff) |
drm/amd/display: No need to keep track of unreffed clk sources
This simplifies clock source reprogramming a bit.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
5 files changed, 16 insertions, 52 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9aa0da743174..15b627548cd2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c | |||
@@ -261,13 +261,12 @@ bool resource_construct( | |||
261 | } | 261 | } |
262 | 262 | ||
263 | 263 | ||
264 | bool resource_unreference_clock_source( | 264 | void resource_unreference_clock_source( |
265 | struct resource_context *res_ctx, | 265 | struct resource_context *res_ctx, |
266 | const struct resource_pool *pool, | 266 | const struct resource_pool *pool, |
267 | struct clock_source *clock_source) | 267 | struct clock_source *clock_source) |
268 | { | 268 | { |
269 | int i; | 269 | int i; |
270 | bool need_reset = false; | ||
271 | 270 | ||
272 | for (i = 0; i < pool->clk_src_count; i++) { | 271 | for (i = 0; i < pool->clk_src_count; i++) { |
273 | if (pool->clock_sources[i] != clock_source) | 272 | if (pool->clock_sources[i] != clock_source) |
@@ -275,24 +274,11 @@ bool resource_unreference_clock_source( | |||
275 | 274 | ||
276 | res_ctx->clock_source_ref_count[i]--; | 275 | res_ctx->clock_source_ref_count[i]--; |
277 | 276 | ||
278 | if (res_ctx->clock_source_ref_count[i] == 0) { | ||
279 | res_ctx->clock_source_changed[i] = true; | ||
280 | need_reset = true; | ||
281 | } | ||
282 | |||
283 | break; | 277 | break; |
284 | } | 278 | } |
285 | 279 | ||
286 | if (pool->dp_clock_source == clock_source) { | 280 | if (pool->dp_clock_source == clock_source) |
287 | res_ctx->dp_clock_source_ref_count--; | 281 | res_ctx->dp_clock_source_ref_count--; |
288 | |||
289 | if (res_ctx->dp_clock_source_ref_count == 0) { | ||
290 | res_ctx->dp_clock_source_changed = true; | ||
291 | need_reset = true; | ||
292 | } | ||
293 | } | ||
294 | |||
295 | return need_reset; | ||
296 | } | 282 | } |
297 | 283 | ||
298 | void resource_reference_clock_source( | 284 | void resource_reference_clock_source( |
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index c57dc45d6677..31592e53f504 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |||
@@ -1640,6 +1640,8 @@ static void dce110_reset_hw_ctx_wrap( | |||
1640 | 1640 | ||
1641 | if (!pipe_ctx->stream || | 1641 | if (!pipe_ctx->stream || |
1642 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { | 1642 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { |
1643 | struct clock_source *old_clk = pipe_ctx_old->clock_source; | ||
1644 | |||
1643 | core_link_disable_stream(pipe_ctx_old); | 1645 | core_link_disable_stream(pipe_ctx_old); |
1644 | pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); | 1646 | pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); |
1645 | if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { | 1647 | if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { |
@@ -1650,27 +1652,14 @@ static void dce110_reset_hw_ctx_wrap( | |||
1650 | pipe_ctx_old->plane_res.mi->funcs->free_mem_input( | 1652 | pipe_ctx_old->plane_res.mi->funcs->free_mem_input( |
1651 | pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); | 1653 | pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); |
1652 | 1654 | ||
1655 | if (old_clk) | ||
1656 | old_clk->funcs->cs_power_down(old_clk); | ||
1657 | |||
1653 | dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); | 1658 | dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); |
1654 | 1659 | ||
1655 | pipe_ctx_old->stream = NULL; | 1660 | pipe_ctx_old->stream = NULL; |
1656 | } | 1661 | } |
1657 | } | 1662 | } |
1658 | |||
1659 | /* power down changed clock sources */ | ||
1660 | for (i = 0; i < dc->res_pool->clk_src_count; i++) | ||
1661 | if (context->res_ctx.clock_source_changed[i]) { | ||
1662 | struct clock_source *clk = dc->res_pool->clock_sources[i]; | ||
1663 | |||
1664 | clk->funcs->cs_power_down(clk); | ||
1665 | context->res_ctx.clock_source_changed[i] = false; | ||
1666 | } | ||
1667 | |||
1668 | if (context->res_ctx.dp_clock_source_changed) { | ||
1669 | struct clock_source *clk = dc->res_pool->dp_clock_source; | ||
1670 | |||
1671 | clk->funcs->cs_power_down(clk); | ||
1672 | context->res_ctx.clock_source_changed[i] = false; | ||
1673 | } | ||
1674 | } | 1663 | } |
1675 | 1664 | ||
1676 | 1665 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 6fee6957c1a6..c8c4b951ee1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |||
@@ -1265,22 +1265,6 @@ static void reset_hw_ctx_wrap( | |||
1265 | plane_atomic_power_down(dc, i); | 1265 | plane_atomic_power_down(dc, i); |
1266 | } | 1266 | } |
1267 | 1267 | ||
1268 | /* power down changed clock sources */ | ||
1269 | for (i = 0; i < dc->res_pool->clk_src_count; i++) | ||
1270 | if (context->res_ctx.clock_source_changed[i]) { | ||
1271 | struct clock_source *clk = dc->res_pool->clock_sources[i]; | ||
1272 | |||
1273 | clk->funcs->cs_power_down(clk); | ||
1274 | context->res_ctx.clock_source_changed[i] = false; | ||
1275 | } | ||
1276 | |||
1277 | if (context->res_ctx.dp_clock_source_changed) { | ||
1278 | struct clock_source *clk = dc->res_pool->dp_clock_source; | ||
1279 | |||
1280 | clk->funcs->cs_power_down(clk); | ||
1281 | context->res_ctx.dp_clock_source_changed = false; | ||
1282 | } | ||
1283 | |||
1284 | /* Reset Back End*/ | 1268 | /* Reset Back End*/ |
1285 | for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { | 1269 | for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { |
1286 | struct pipe_ctx *pipe_ctx_old = | 1270 | struct pipe_ctx *pipe_ctx_old = |
@@ -1291,9 +1275,16 @@ static void reset_hw_ctx_wrap( | |||
1291 | continue; | 1275 | continue; |
1292 | 1276 | ||
1293 | if (!pipe_ctx->stream || | 1277 | if (!pipe_ctx->stream || |
1294 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) | 1278 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { |
1279 | struct clock_source *old_clk = pipe_ctx_old->clock_source; | ||
1280 | |||
1295 | reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); | 1281 | reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); |
1282 | |||
1283 | if (old_clk) | ||
1284 | old_clk->funcs->cs_power_down(old_clk); | ||
1285 | } | ||
1296 | } | 1286 | } |
1287 | |||
1297 | } | 1288 | } |
1298 | 1289 | ||
1299 | static bool patch_address_for_sbs_tb_stereo( | 1290 | static bool patch_address_for_sbs_tb_stereo( |
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b6a513d6feda..915d5c10361b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h | |||
@@ -213,9 +213,7 @@ struct resource_context { | |||
213 | bool is_stream_enc_acquired[MAX_PIPES * 2]; | 213 | bool is_stream_enc_acquired[MAX_PIPES * 2]; |
214 | bool is_audio_acquired[MAX_PIPES]; | 214 | bool is_audio_acquired[MAX_PIPES]; |
215 | uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; | 215 | uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; |
216 | bool clock_source_changed[MAX_CLOCK_SOURCES]; | ||
217 | uint8_t dp_clock_source_ref_count; | 216 | uint8_t dp_clock_source_ref_count; |
218 | bool dp_clock_source_changed; | ||
219 | }; | 217 | }; |
220 | 218 | ||
221 | struct dce_bw_output { | 219 | struct dce_bw_output { |
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index cf1797c191e9..614bb691ab59 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h | |||
@@ -92,7 +92,7 @@ enum dc_status resource_build_scaling_params_for_context( | |||
92 | 92 | ||
93 | void resource_build_info_frame(struct pipe_ctx *pipe_ctx); | 93 | void resource_build_info_frame(struct pipe_ctx *pipe_ctx); |
94 | 94 | ||
95 | bool resource_unreference_clock_source( | 95 | void resource_unreference_clock_source( |
96 | struct resource_context *res_ctx, | 96 | struct resource_context *res_ctx, |
97 | const struct resource_pool *pool, | 97 | const struct resource_pool *pool, |
98 | struct clock_source *clock_source); | 98 | struct clock_source *clock_source); |