aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorAntoine Tenart <antoine.tenart@bootlin.com>2019-05-29 09:59:48 -0400
committerDavid S. Miller <davem@davemloft.net>2019-05-30 17:31:13 -0400
commit21808437214637952b61beaba6034d97880fbeb3 (patch)
treea34d2d49a42e43ef2cba4bf40fd5cf1497440200 /drivers
parent9609dad263f8bea347f41fddca29353dbf8a7d37 (diff)
net: mvpp2: fix bad MVPP2_TXQ_SCHED_TOKEN_CNTR_REG queue value
MVPP2_TXQ_SCHED_TOKEN_CNTR_REG() expects the logical queue id but the current code is passing the global tx queue offset, so it ends up writing to unknown registers (between 0x8280 and 0x82fc, which seemed to be unused by the hardware). This fixes the issue by using the logical queue id instead. Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network unit") Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index d38952eb7aa9..7a67e23a2c2b 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1455,7 +1455,7 @@ static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1455/* Set defaults to the MVPP2 port */ 1455/* Set defaults to the MVPP2 port */
1456static void mvpp2_defaults_set(struct mvpp2_port *port) 1456static void mvpp2_defaults_set(struct mvpp2_port *port)
1457{ 1457{
1458 int tx_port_num, val, queue, ptxq, lrxq; 1458 int tx_port_num, val, queue, lrxq;
1459 1459
1460 if (port->priv->hw_version == MVPP21) { 1460 if (port->priv->hw_version == MVPP21) {
1461 /* Update TX FIFO MIN Threshold */ 1461 /* Update TX FIFO MIN Threshold */
@@ -1476,11 +1476,9 @@ static void mvpp2_defaults_set(struct mvpp2_port *port)
1476 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1476 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1477 1477
1478 /* Close bandwidth for all queues */ 1478 /* Close bandwidth for all queues */
1479 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { 1479 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
1480 ptxq = mvpp2_txq_phys(port->id, queue);
1481 mvpp2_write(port->priv, 1480 mvpp2_write(port->priv,
1482 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); 1481 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
1483 }
1484 1482
1485 /* Set refill period to 1 usec, refill tokens 1483 /* Set refill period to 1 usec, refill tokens
1486 * and bucket size to maximum 1484 * and bucket size to maximum
@@ -2336,7 +2334,7 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port,
2336 txq->descs_dma = 0; 2334 txq->descs_dma = 0;
2337 2335
2338 /* Set minimum bandwidth for disabled TXQs */ 2336 /* Set minimum bandwidth for disabled TXQs */
2339 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); 2337 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
2340 2338
2341 /* Set Tx descriptors queue starting address and size */ 2339 /* Set Tx descriptors queue starting address and size */
2342 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2340 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());