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authorJordan Crouse <jcrouse@codeaurora.org>2017-11-21 14:40:53 -0500
committerRob Clark <robdclark@gmail.com>2018-01-10 08:58:42 -0500
commit1babd706b455802d17762cb44ecdfcd953bb3dd5 (patch)
tree678b3f5ef23518fcf720673a1d4c61d032e0f30d /drivers
parent156a537d056aa9057d1e2d94e5a81505580000bd (diff)
drm/msm/gpu: Remove unused bus scaling code
Remove the downstream bus scaling code. It isn't needed for for compatibility with a downstream or vendor kernel. Get it out of the way to clear space for devfreq support. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_gpu.c7
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_gpu.h5
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.c39
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.h7
4 files changed, 3 insertions, 55 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 2f0610f8fc8d..61e3091fada9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -480,13 +480,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
480 adreno_gpu->rev = config->rev; 480 adreno_gpu->rev = config->rev;
481 481
482 gpu->fast_rate = config->fast_rate; 482 gpu->fast_rate = config->fast_rate;
483 gpu->bus_freq = config->bus_freq;
484#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
485 gpu->bus_scale_table = config->bus_scale_table;
486#endif
487 483
488 DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u", 484 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
489 gpu->fast_rate, gpu->bus_freq);
490 485
491 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 486 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
492 adreno_gpu_config.irqname = "kgsl_3d0_irq"; 487 adreno_gpu_config.irqname = "kgsl_3d0_irq";
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 28e3de6e5f94..88d1bdfd9aae 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -129,10 +129,7 @@ struct adreno_gpu {
129/* platform config data (ie. from DT, or pdata) */ 129/* platform config data (ie. from DT, or pdata) */
130struct adreno_platform_config { 130struct adreno_platform_config {
131 struct adreno_rev rev; 131 struct adreno_rev rev;
132 uint32_t fast_rate, bus_freq; 132 uint32_t fast_rate;
133#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
134 struct msm_bus_scale_pdata *bus_scale_table;
135#endif
136}; 133};
137 134
138#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 135#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 6fbc2fc259ce..5416fe85d816 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -27,37 +27,6 @@
27 * Power Management: 27 * Power Management:
28 */ 28 */
29 29
30#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
31#include <mach/board.h>
32static void bs_init(struct msm_gpu *gpu)
33{
34 if (gpu->bus_scale_table) {
35 gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
36 DBG("bus scale client: %08x", gpu->bsc);
37 }
38}
39
40static void bs_fini(struct msm_gpu *gpu)
41{
42 if (gpu->bsc) {
43 msm_bus_scale_unregister_client(gpu->bsc);
44 gpu->bsc = 0;
45 }
46}
47
48static void bs_set(struct msm_gpu *gpu, int idx)
49{
50 if (gpu->bsc) {
51 DBG("set bus scaling: %d", idx);
52 msm_bus_scale_client_update_request(gpu->bsc, idx);
53 }
54}
55#else
56static void bs_init(struct msm_gpu *gpu) {}
57static void bs_fini(struct msm_gpu *gpu) {}
58static void bs_set(struct msm_gpu *gpu, int idx) {}
59#endif
60
61static int enable_pwrrail(struct msm_gpu *gpu) 30static int enable_pwrrail(struct msm_gpu *gpu)
62{ 31{
63 struct drm_device *dev = gpu->dev; 32 struct drm_device *dev = gpu->dev;
@@ -143,8 +112,6 @@ static int enable_axi(struct msm_gpu *gpu)
143{ 112{
144 if (gpu->ebi1_clk) 113 if (gpu->ebi1_clk)
145 clk_prepare_enable(gpu->ebi1_clk); 114 clk_prepare_enable(gpu->ebi1_clk);
146 if (gpu->bus_freq)
147 bs_set(gpu, gpu->bus_freq);
148 return 0; 115 return 0;
149} 116}
150 117
@@ -152,8 +119,6 @@ static int disable_axi(struct msm_gpu *gpu)
152{ 119{
153 if (gpu->ebi1_clk) 120 if (gpu->ebi1_clk)
154 clk_disable_unprepare(gpu->ebi1_clk); 121 clk_disable_unprepare(gpu->ebi1_clk);
155 if (gpu->bus_freq)
156 bs_set(gpu, 0);
157 return 0; 122 return 0;
158} 123}
159 124
@@ -755,8 +720,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
755 gpu->pdev = pdev; 720 gpu->pdev = pdev;
756 platform_set_drvdata(pdev, gpu); 721 platform_set_drvdata(pdev, gpu);
757 722
758 bs_init(gpu);
759
760 gpu->aspace = msm_gpu_create_address_space(gpu, pdev, 723 gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
761 config->va_start, config->va_end); 724 config->va_start, config->va_end);
762 725
@@ -826,8 +789,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
826 789
827 WARN_ON(!list_empty(&gpu->active_list)); 790 WARN_ON(!list_empty(&gpu->active_list));
828 791
829 bs_fini(gpu);
830
831 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 792 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
832 msm_ringbuffer_destroy(gpu->rb[i]); 793 msm_ringbuffer_destroy(gpu->rb[i]);
833 gpu->rb[i] = NULL; 794 gpu->rb[i] = NULL;
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index e113d64574d3..0de26b6f3732 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -108,12 +108,7 @@ struct msm_gpu {
108 struct clk **grp_clks; 108 struct clk **grp_clks;
109 int nr_clocks; 109 int nr_clocks;
110 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; 110 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
111 uint32_t fast_rate, bus_freq; 111 uint32_t fast_rate;
112
113#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
114 struct msm_bus_scale_pdata *bus_scale_table;
115 uint32_t bsc;
116#endif
117 112
118 /* Hang and Inactivity Detection: 113 /* Hang and Inactivity Detection:
119 */ 114 */