drm/omap: HDMI5: Add interlace support

Add the missing bits for interlace:

* Set VBLANK_OSC if the videomode's vblank is fractional
* Halve the vertical timings for interlace
* Double the horizontal timings for double-pixel mode
* Set FC_PRCONF properly for double-pixel mode

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

1 files changed, 26 insertions, 1 deletions

diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 947edb9d4275..6a397520cae5 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -298,10 +298,30 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
         video_cfg->data_enable_pol = 1; /* It is always 1*/
         video_cfg->hblank = cfg->timings.hfp +
                                 cfg->timings.hbp + cfg->timings.hsw;
-        video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
+        video_cfg->vblank_osc = 0;
         video_cfg->vblank = cfg->timings.vsw +
                                 cfg->timings.vfp + cfg->timings.vbp;
         video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
+
+        if (cfg->timings.interlace) {
+                /* set vblank_osc if vblank is fractional */
+                if (video_cfg->vblank % 2 != 0)
+                        video_cfg->vblank_osc = 1;
+
+                video_cfg->v_fc_config.timings.y_res /= 2;
+                video_cfg->vblank /= 2;
+                video_cfg->v_fc_config.timings.vfp /= 2;
+                video_cfg->v_fc_config.timings.vsw /= 2;
+                video_cfg->v_fc_config.timings.vbp /= 2;
+        }
+
+        if (cfg->timings.double_pixel) {
+                video_cfg->v_fc_config.timings.x_res *= 2;
+                video_cfg->hblank *= 2;
+                video_cfg->v_fc_config.timings.hfp *= 2;
+                video_cfg->v_fc_config.timings.hsw *= 2;
+                video_cfg->v_fc_config.timings.hbp *= 2;
+        }
 }
 
 /* DSS_HDMI_CORE_VIDEO_CONFIG */
@@ -368,6 +388,11 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
         /* select DVI mode */
         REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
                         cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
+
+        if (cfg->v_fc_config.timings.double_pixel)
+                REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
+        else
+                REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
 }
 
 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)