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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-09-21 14:01:16 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-09-21 14:01:16 -0400
commit10dc890d4228cd17ddfd09ba9aaa9221627e29b2 (patch)
treeeaef8353d6e93b010e25836fc6e40c5bc439ab66 /drivers
parenta27fb6d983c7b5bb0129ae4d7a7c81758173bfab (diff)
parent96147db1e1dff83679e71ac92193cbcab761a14c (diff)
Merge tag 'pinctrl-v4.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Linus writes: "Pin control fixes for v4.19: - Two fixes for the Intel pin controllers than cause problems on laptops." * tag 'pinctrl-v4.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: intel: Do pin translation in other GPIO operations as well pinctrl: cannonlake: Fix gpio base for GPP-E
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/intel/pinctrl-cannonlake.c2
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c111
2 files changed, 64 insertions, 49 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index fb1afe55bf53..8d48371caaa2 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -379,7 +379,7 @@ static const struct intel_padgroup cnlh_community1_gpps[] = {
379static const struct intel_padgroup cnlh_community3_gpps[] = { 379static const struct intel_padgroup cnlh_community3_gpps[] = {
380 CNL_GPP(0, 155, 178, 192), /* GPP_K */ 380 CNL_GPP(0, 155, 178, 192), /* GPP_K */
381 CNL_GPP(1, 179, 202, 224), /* GPP_H */ 381 CNL_GPP(1, 179, 202, 224), /* GPP_H */
382 CNL_GPP(2, 203, 215, 258), /* GPP_E */ 382 CNL_GPP(2, 203, 215, 256), /* GPP_E */
383 CNL_GPP(3, 216, 239, 288), /* GPP_F */ 383 CNL_GPP(3, 216, 239, 288), /* GPP_F */
384 CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */ 384 CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */
385}; 385};
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 62b009b27eda..ec8dafc94694 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -747,13 +747,63 @@ static const struct pinctrl_desc intel_pinctrl_desc = {
747 .owner = THIS_MODULE, 747 .owner = THIS_MODULE,
748}; 748};
749 749
750/**
751 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
752 * @pctrl: Pinctrl structure
753 * @offset: GPIO offset from gpiolib
754 * @commmunity: Community is filled here if not %NULL
755 * @padgrp: Pad group is filled here if not %NULL
756 *
757 * When coming through gpiolib irqchip, the GPIO offset is not
758 * automatically translated to pinctrl pin number. This function can be
759 * used to find out the corresponding pinctrl pin.
760 */
761static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
762 const struct intel_community **community,
763 const struct intel_padgroup **padgrp)
764{
765 int i;
766
767 for (i = 0; i < pctrl->ncommunities; i++) {
768 const struct intel_community *comm = &pctrl->communities[i];
769 int j;
770
771 for (j = 0; j < comm->ngpps; j++) {
772 const struct intel_padgroup *pgrp = &comm->gpps[j];
773
774 if (pgrp->gpio_base < 0)
775 continue;
776
777 if (offset >= pgrp->gpio_base &&
778 offset < pgrp->gpio_base + pgrp->size) {
779 int pin;
780
781 pin = pgrp->base + offset - pgrp->gpio_base;
782 if (community)
783 *community = comm;
784 if (padgrp)
785 *padgrp = pgrp;
786
787 return pin;
788 }
789 }
790 }
791
792 return -EINVAL;
793}
794
750static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 795static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
751{ 796{
752 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 797 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
753 void __iomem *reg; 798 void __iomem *reg;
754 u32 padcfg0; 799 u32 padcfg0;
800 int pin;
801
802 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
803 if (pin < 0)
804 return -EINVAL;
755 805
756 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 806 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
757 if (!reg) 807 if (!reg)
758 return -EINVAL; 808 return -EINVAL;
759 809
@@ -770,8 +820,13 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
770 unsigned long flags; 820 unsigned long flags;
771 void __iomem *reg; 821 void __iomem *reg;
772 u32 padcfg0; 822 u32 padcfg0;
823 int pin;
824
825 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
826 if (pin < 0)
827 return;
773 828
774 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 829 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
775 if (!reg) 830 if (!reg)
776 return; 831 return;
777 832
@@ -790,8 +845,13 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
790 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 845 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
791 void __iomem *reg; 846 void __iomem *reg;
792 u32 padcfg0; 847 u32 padcfg0;
848 int pin;
793 849
794 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 850 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
851 if (pin < 0)
852 return -EINVAL;
853
854 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
795 if (!reg) 855 if (!reg)
796 return -EINVAL; 856 return -EINVAL;
797 857
@@ -827,51 +887,6 @@ static const struct gpio_chip intel_gpio_chip = {
827 .set_config = gpiochip_generic_config, 887 .set_config = gpiochip_generic_config,
828}; 888};
829 889
830/**
831 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
832 * @pctrl: Pinctrl structure
833 * @offset: GPIO offset from gpiolib
834 * @commmunity: Community is filled here if not %NULL
835 * @padgrp: Pad group is filled here if not %NULL
836 *
837 * When coming through gpiolib irqchip, the GPIO offset is not
838 * automatically translated to pinctrl pin number. This function can be
839 * used to find out the corresponding pinctrl pin.
840 */
841static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
842 const struct intel_community **community,
843 const struct intel_padgroup **padgrp)
844{
845 int i;
846
847 for (i = 0; i < pctrl->ncommunities; i++) {
848 const struct intel_community *comm = &pctrl->communities[i];
849 int j;
850
851 for (j = 0; j < comm->ngpps; j++) {
852 const struct intel_padgroup *pgrp = &comm->gpps[j];
853
854 if (pgrp->gpio_base < 0)
855 continue;
856
857 if (offset >= pgrp->gpio_base &&
858 offset < pgrp->gpio_base + pgrp->size) {
859 int pin;
860
861 pin = pgrp->base + offset - pgrp->gpio_base;
862 if (community)
863 *community = comm;
864 if (padgrp)
865 *padgrp = pgrp;
866
867 return pin;
868 }
869 }
870 }
871
872 return -EINVAL;
873}
874
875static int intel_gpio_irq_reqres(struct irq_data *d) 890static int intel_gpio_irq_reqres(struct irq_data *d)
876{ 891{
877 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 892 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);