diff options
| author | Matthew McClintock <mmcclint@codeaurora.org> | 2016-06-28 14:35:21 -0400 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2016-07-17 15:03:14 -0400 |
| commit | 10073a205df269abcbd9c3fbc690a813827107ef (patch) | |
| tree | 69c908c71c3418f3253d7e6f3242964195f0da27 /drivers/watchdog/qcom-wdt.c | |
| parent | f0d9d0f4b44ae5503ea368e7f066b20f12ca1d37 (diff) | |
watchdog: qcom: configure BARK time in addition to BITE time
For certain parts and some versions of TZ, TZ will reset the chip
when a BARK is triggered even though it was not configured here. So
by default let's configure this BARK time as well.
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/watchdog/qcom-wdt.c')
| -rw-r--r-- | drivers/watchdog/qcom-wdt.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index 111e8a7d2645..5796b5d1b3f2 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c | |||
| @@ -24,6 +24,7 @@ enum wdt_reg { | |||
| 24 | WDT_RST, | 24 | WDT_RST, |
| 25 | WDT_EN, | 25 | WDT_EN, |
| 26 | WDT_STS, | 26 | WDT_STS, |
| 27 | WDT_BARK_TIME, | ||
| 27 | WDT_BITE_TIME, | 28 | WDT_BITE_TIME, |
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| @@ -31,6 +32,7 @@ static const u32 reg_offset_data_apcs_tmr[] = { | |||
| 31 | [WDT_RST] = 0x38, | 32 | [WDT_RST] = 0x38, |
| 32 | [WDT_EN] = 0x40, | 33 | [WDT_EN] = 0x40, |
| 33 | [WDT_STS] = 0x44, | 34 | [WDT_STS] = 0x44, |
| 35 | [WDT_BARK_TIME] = 0x4C, | ||
| 34 | [WDT_BITE_TIME] = 0x5C, | 36 | [WDT_BITE_TIME] = 0x5C, |
| 35 | }; | 37 | }; |
| 36 | 38 | ||
| @@ -38,6 +40,7 @@ static const u32 reg_offset_data_kpss[] = { | |||
| 38 | [WDT_RST] = 0x4, | 40 | [WDT_RST] = 0x4, |
| 39 | [WDT_EN] = 0x8, | 41 | [WDT_EN] = 0x8, |
| 40 | [WDT_STS] = 0xC, | 42 | [WDT_STS] = 0xC, |
| 43 | [WDT_BARK_TIME] = 0x10, | ||
| 41 | [WDT_BITE_TIME] = 0x14, | 44 | [WDT_BITE_TIME] = 0x14, |
| 42 | }; | 45 | }; |
| 43 | 46 | ||
| @@ -66,6 +69,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd) | |||
| 66 | 69 | ||
| 67 | writel(0, wdt_addr(wdt, WDT_EN)); | 70 | writel(0, wdt_addr(wdt, WDT_EN)); |
| 68 | writel(1, wdt_addr(wdt, WDT_RST)); | 71 | writel(1, wdt_addr(wdt, WDT_RST)); |
| 72 | writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); | ||
| 69 | writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); | 73 | writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); |
| 70 | writel(1, wdt_addr(wdt, WDT_EN)); | 74 | writel(1, wdt_addr(wdt, WDT_EN)); |
| 71 | return 0; | 75 | return 0; |
| @@ -108,6 +112,7 @@ static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, | |||
| 108 | 112 | ||
| 109 | writel(0, wdt_addr(wdt, WDT_EN)); | 113 | writel(0, wdt_addr(wdt, WDT_EN)); |
| 110 | writel(1, wdt_addr(wdt, WDT_RST)); | 114 | writel(1, wdt_addr(wdt, WDT_RST)); |
| 115 | writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); | ||
| 111 | writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); | 116 | writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); |
| 112 | writel(1, wdt_addr(wdt, WDT_EN)); | 117 | writel(1, wdt_addr(wdt, WDT_EN)); |
| 113 | 118 | ||