USB: EHCI: split ehci_qh into hw and sw parts

The ehci_qh structure merged hw and sw together which is not good:
1. More and more items are being added into ehci_qh, the ehci_qh software
   part are unnecessary to be allocated in DMA qh_pool.
2. If HCD has local SRAM, the sw part will consume it too, and it won't
   bring any benefit.
3. For non-cache-coherence system, the entire ehci_qh is uncachable, actually
   we only need the hw part to be uncacheable. Spliting them will let the sw
   part to be cacheable.

Signed-off-by: Alek Du <alek.du@intel.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
CC: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 8 insertions, 6 deletions

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2dc15f3ad143..7bee1638dfd7 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -507,6 +507,7 @@ static int ehci_init(struct usb_hcd *hcd)
         u32                     temp;
         int                     retval;
         u32                     hcc_params;
+        struct ehci_qh_hw       *hw;
 
         spin_lock_init(&ehci->lock);
 
@@ -550,12 +551,13 @@ static int ehci_init(struct usb_hcd *hcd)
          * from automatically advancing to the next td after short reads.
          */
         ehci->async->qh_next.qh = NULL;
-        ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
-        ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
-        ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
-        ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
+        hw = ehci->async->hw;
+        hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
+        hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
+        hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
+        hw->hw_qtd_next = EHCI_LIST_END(ehci);
         ehci->async->qh_state = QH_STATE_LINKED;
-        ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
+        hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
 
         /* clear interrupt enables, set irq latency */
         if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
@@ -985,7 +987,7 @@ rescan:
         /* endpoints can be iso streams.  for now, we don't
          * accelerate iso completions ... so spin a while.
          */
-        if (qh->hw_info1 == 0) {
+        if (qh->hw->hw_info1 == 0) {
                 ehci_vdbg (ehci, "iso delay\n");
                 goto idle_timeout;
         }