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authorDouglas Anderson <dianders@chromium.org>2016-01-28 21:20:12 -0500
committerFelipe Balbi <balbi@kernel.org>2016-03-04 08:14:45 -0500
commit9f9f09b048f5fdfded26149defd61b737b314ba0 (patch)
tree934d7d7ccbcf1e53d7fbc3a01418eb62fbfcb4ca /drivers/usb/dwc2/hcd_queue.c
parent9cf1a601d2affe9c2633ac47ac875c035dd1eb69 (diff)
usb: dwc2: host: Totally redo the microframe scheduler
This totally reimplements the microframe scheduler in dwc2 to attempt to handle periodic splits properly. The old code didn't even try, so this was a significant effort since periodic splits are one of the most complicated things in USB. I've attempted to keep the old "don't use the microframe" schduler around for now, but not sure it's needed. It has also only been lightly tested. I think it's pretty certain that this scheduler isn't perfect and might have some bugs, but it seems much better than what was there before. With this change my stressful USB test (USB webcam + USB audio + some keyboards) crackles less. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
Diffstat (limited to 'drivers/usb/dwc2/hcd_queue.c')
-rw-r--r--drivers/usb/dwc2/hcd_queue.c1170
1 files changed, 1010 insertions, 160 deletions
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
index 76f3c6596bef..7f634fd771c7 100644
--- a/drivers/usb/dwc2/hcd_queue.c
+++ b/drivers/usb/dwc2/hcd_queue.c
@@ -136,116 +136,933 @@ static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
136} 136}
137 137
138/** 138/**
139 * Microframe scheduler 139 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
140 * track the total use in hsotg->frame_usecs 140 *
141 * keep each qh use in qh->frame_usecs 141 * @map: The bitmap representing the schedule; will be updated
142 * when surrendering the qh then donate the time back 142 * upon success.
143 * @bits_per_period: The schedule represents several periods. This is how many
144 * bits are in each period. It's assumed that the beginning
145 * of the schedule will repeat after its end.
146 * @periods_in_map: The number of periods in the schedule.
147 * @num_bits: The number of bits we need per period we want to reserve
148 * in this function call.
149 * @interval: How often we need to be scheduled for the reservation this
150 * time. 1 means every period. 2 means every other period.
151 * ...you get the picture?
152 * @start: The bit number to start at. Normally 0. Must be within
153 * the interval or we return failure right away.
154 * @only_one_period: Normally we'll allow picking a start anywhere within the
155 * first interval, since we can still make all repetition
156 * requirements by doing that. However, if you pass true
157 * here then we'll return failure if we can't fit within
158 * the period that "start" is in.
159 *
160 * The idea here is that we want to schedule time for repeating events that all
161 * want the same resource. The resource is divided into fixed-sized periods
162 * and the events want to repeat every "interval" periods. The schedule
163 * granularity is one bit.
164 *
165 * To keep things "simple", we'll represent our schedule with a bitmap that
166 * contains a fixed number of periods. This gets rid of a lot of complexity
167 * but does mean that we need to handle things specially (and non-ideally) if
168 * the number of the periods in the schedule doesn't match well with the
169 * intervals that we're trying to schedule.
170 *
171 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
172 * - If interval is 1, we need to take up space in each of the 8
173 * periods we're scheduling. Easy.
174 * - If interval is 2, we need to take up space in half of the
175 * periods. Again, easy.
176 * - If interval is 3, we actually need to fall back to interval 1.
177 * Why? Because we might need time in any period. AKA for the
178 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
179 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
180 * 0, 3, and 6. Since we could be in any frame we need to reserve
181 * for all of them. Sucks, but that's what you gotta do. Note that
182 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
183 * then we need more memory and time to do scheduling.
184 * - If interval is 4, easy.
185 * - If interval is 5, we again need interval 1. The schedule will be
186 * 0, 5, 2, 7, 4, 1, 6, 3, 0
187 * - If interval is 6, we need interval 2. 0, 6, 4, 2.
188 * - If interval is 7, we need interval 1.
189 * - If interval is 8, we need interval 8.
190 *
191 * If you do the math, you'll see that we need to pretend that interval is
192 * equal to the greatest_common_divisor(interval, periods_in_map).
193 *
194 * Note that at the moment this function tends to front-pack the schedule.
195 * In some cases that's really non-ideal (it's hard to schedule things that
196 * need to repeat every period). In other cases it's perfect (you can easily
197 * schedule bigger, less often repeating things).
198 *
199 * Here's the algorithm in action (8 periods, 5 bits per period):
200 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
201 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
202 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
203 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
204 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
205 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
206 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
207 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
208 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
209 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
210 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
211 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
212 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
213 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
214 * | | | | | | | | | Remv 1 bits, intv 1 at 4
215 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
216 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
217 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
218 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
219 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
220 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
221 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
222 *
223 * This function is pretty generic and could be easily abstracted if anything
224 * needed similar scheduling.
225 *
226 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
227 * unschedule routine. The map bitmap will be updated on a non-error result.
143 */ 228 */
144static const unsigned short max_uframe_usecs[] = { 229static int pmap_schedule(unsigned long *map, int bits_per_period,
145 100, 100, 100, 100, 100, 100, 30, 0 230 int periods_in_map, int num_bits,
146}; 231 int interval, int start, bool only_one_period)
232{
233 int interval_bits;
234 int to_reserve;
235 int first_end;
236 int i;
237
238 if (num_bits > bits_per_period)
239 return -ENOSPC;
240
241 /* Adjust interval as per description */
242 interval = gcd(interval, periods_in_map);
243
244 interval_bits = bits_per_period * interval;
245 to_reserve = periods_in_map / interval;
246
247 /* If start has gotten us past interval then we can't schedule */
248 if (start >= interval_bits)
249 return -ENOSPC;
250
251 if (only_one_period)
252 /* Must fit within same period as start; end at begin of next */
253 first_end = (start / bits_per_period + 1) * bits_per_period;
254 else
255 /* Can fit anywhere in the first interval */
256 first_end = interval_bits;
257
258 /*
259 * We'll try to pick the first repetition, then see if that time
260 * is free for each of the subsequent repetitions. If it's not
261 * we'll adjust the start time for the next search of the first
262 * repetition.
263 */
264 while (start + num_bits <= first_end) {
265 int end;
266
267 /* Need to stay within this period */
268 end = (start / bits_per_period + 1) * bits_per_period;
269
270 /* Look for num_bits us in this microframe starting at start */
271 start = bitmap_find_next_zero_area(map, end, start, num_bits,
272 0);
273
274 /*
275 * We should get start >= end if we fail. We might be
276 * able to check the next microframe depending on the
277 * interval, so continue on (start already updated).
278 */
279 if (start >= end) {
280 start = end;
281 continue;
282 }
283
284 /* At this point we have a valid point for first one */
285 for (i = 1; i < to_reserve; i++) {
286 int ith_start = start + interval_bits * i;
287 int ith_end = end + interval_bits * i;
288 int ret;
289
290 /* Use this as a dumb "check if bits are 0" */
291 ret = bitmap_find_next_zero_area(
292 map, ith_start + num_bits, ith_start, num_bits,
293 0);
294
295 /* We got the right place, continue checking */
296 if (ret == ith_start)
297 continue;
298
299 /* Move start up for next time and exit for loop */
300 ith_start = bitmap_find_next_zero_area(
301 map, ith_end, ith_start, num_bits, 0);
302 if (ith_start >= ith_end)
303 /* Need a while new period next time */
304 start = end;
305 else
306 start = ith_start - interval_bits * i;
307 break;
308 }
309
310 /* If didn't exit the for loop with a break, we have success */
311 if (i == to_reserve)
312 break;
313 }
314
315 if (start + num_bits > first_end)
316 return -ENOSPC;
147 317
148void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 318 for (i = 0; i < to_reserve; i++) {
319 int ith_start = start + interval_bits * i;
320
321 bitmap_set(map, ith_start, num_bits);
322 }
323
324 return start;
325}
326
327/**
328 * pmap_unschedule() - Undo work done by pmap_schedule()
329 *
330 * @map: See pmap_schedule().
331 * @bits_per_period: See pmap_schedule().
332 * @periods_in_map: See pmap_schedule().
333 * @num_bits: The number of bits that was passed to schedule.
334 * @interval: The interval that was passed to schedule.
335 * @start: The return value from pmap_schedule().
336 */
337static void pmap_unschedule(unsigned long *map, int bits_per_period,
338 int periods_in_map, int num_bits,
339 int interval, int start)
149{ 340{
341 int interval_bits;
342 int to_release;
150 int i; 343 int i;
151 344
152 for (i = 0; i < 8; i++) 345 /* Adjust interval as per description in pmap_schedule() */
153 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 346 interval = gcd(interval, periods_in_map);
347
348 interval_bits = bits_per_period * interval;
349 to_release = periods_in_map / interval;
350
351 for (i = 0; i < to_release; i++) {
352 int ith_start = start + interval_bits * i;
353
354 bitmap_clear(map, ith_start, num_bits);
355 }
154} 356}
155 357
156static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 358/*
359 * cat_printf() - A printf() + strcat() helper
360 *
361 * This is useful for concatenating a bunch of strings where each string is
362 * constructed using printf.
363 *
364 * @buf: The destination buffer; will be updated to point after the printed
365 * data.
366 * @size: The number of bytes in the buffer (includes space for '\0').
367 * @fmt: The format for printf.
368 * @...: The args for printf.
369 */
370static void cat_printf(char **buf, size_t *size, const char *fmt, ...)
157{ 371{
158 unsigned short utime = qh->host_us; 372 va_list args;
159 int i; 373 int i;
160 374
161 for (i = 0; i < 8; i++) { 375 if (*size == 0)
162 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 376 return;
163 if (utime <= hsotg->frame_usecs[i]) { 377
164 hsotg->frame_usecs[i] -= utime; 378 va_start(args, fmt);
165 qh->frame_usecs[i] += utime; 379 i = vsnprintf(*buf, *size, fmt, args);
166 return i; 380 va_end(args);
167 } 381
382 if (i >= *size) {
383 (*buf)[*size - 1] = '\0';
384 *buf += *size;
385 *size = 0;
386 } else {
387 *buf += i;
388 *size -= i;
168 } 389 }
169 return -ENOSPC;
170} 390}
171 391
172/* 392/*
173 * use this for FS apps that can span multiple uframes 393 * pmap_print() - Print the given periodic map
394 *
395 * Will attempt to print out the periodic schedule.
396 *
397 * @map: See pmap_schedule().
398 * @bits_per_period: See pmap_schedule().
399 * @periods_in_map: See pmap_schedule().
400 * @period_name: The name of 1 period, like "uFrame"
401 * @units: The name of the units, like "us".
402 * @print_fn: The function to call for printing.
403 * @print_data: Opaque data to pass to the print function.
174 */ 404 */
175static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 405static void pmap_print(unsigned long *map, int bits_per_period,
406 int periods_in_map, const char *period_name,
407 const char *units,
408 void (*print_fn)(const char *str, void *data),
409 void *print_data)
176{ 410{
177 unsigned short utime = qh->host_us; 411 int period;
178 unsigned short xtime; 412
179 int t_left; 413 for (period = 0; period < periods_in_map; period++) {
414 char tmp[64];
415 char *buf = tmp;
416 size_t buf_size = sizeof(tmp);
417 int period_start = period * bits_per_period;
418 int period_end = period_start + bits_per_period;
419 int start = 0;
420 int count = 0;
421 bool printed = false;
422 int i;
423
424 for (i = period_start; i < period_end + 1; i++) {
425 /* Handle case when ith bit is set */
426 if (i < period_end &&
427 bitmap_find_next_zero_area(map, i + 1,
428 i, 1, 0) != i) {
429 if (count == 0)
430 start = i - period_start;
431 count++;
432 continue;
433 }
434
435 /* ith bit isn't set; don't care if count == 0 */
436 if (count == 0)
437 continue;
438
439 if (!printed)
440 cat_printf(&buf, &buf_size, "%s %d: ",
441 period_name, period);
442 else
443 cat_printf(&buf, &buf_size, ", ");
444 printed = true;
445
446 cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
447 units, start + count - 1, units);
448 count = 0;
449 }
450
451 if (printed)
452 print_fn(tmp, print_data);
453 }
454}
455
456/**
457 * dwc2_get_ls_map() - Get the map used for the given qh
458 *
459 * @hsotg: The HCD state structure for the DWC OTG controller.
460 * @qh: QH for the periodic transfer.
461 *
462 * We'll always get the periodic map out of our TT. Note that even if we're
463 * running the host straight in low speed / full speed mode it appears as if
464 * a TT is allocated for us, so we'll use it. If that ever changes we can
465 * add logic here to get a map out of "hsotg" if !qh->do_split.
466 *
467 * Returns: the map or NULL if a map couldn't be found.
468 */
469static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
470 struct dwc2_qh *qh)
471{
472 unsigned long *map;
473
474 /* Don't expect to be missing a TT and be doing low speed scheduling */
475 if (WARN_ON(!qh->dwc_tt))
476 return NULL;
477
478 /* Get the map and adjust if this is a multi_tt hub */
479 map = qh->dwc_tt->periodic_bitmaps;
480 if (qh->dwc_tt->usb_tt->multi)
481 map += DWC2_ELEMENTS_PER_LS_BITMAP * qh->ttport;
482
483 return map;
484}
485
486struct dwc2_qh_print_data {
487 struct dwc2_hsotg *hsotg;
488 struct dwc2_qh *qh;
489};
490
491/**
492 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
493 *
494 * @str: The string to print
495 * @data: A pointer to a struct dwc2_qh_print_data
496 */
497static void dwc2_qh_print(const char *str, void *data)
498{
499 struct dwc2_qh_print_data *print_data = data;
500
501 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
502}
503
504/**
505 * dwc2_qh_schedule_print() - Print the periodic schedule
506 *
507 * @hsotg: The HCD state structure for the DWC OTG controller.
508 * @qh: QH to print.
509 */
510static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
511 struct dwc2_qh *qh)
512{
513 struct dwc2_qh_print_data print_data = { hsotg, qh };
180 int i; 514 int i;
181 int j;
182 int k;
183 515
184 for (i = 0; i < 8; i++) { 516 /*
185 if (hsotg->frame_usecs[i] <= 0) 517 * The printing functions are quite slow and inefficient.
518 * If we don't have tracing turned on, don't run unless the special
519 * define is turned on.
520 */
521#ifndef DWC2_PRINT_SCHEDULE
522 return;
523#endif
524
525 if (qh->schedule_low_speed) {
526 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
527
528 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
529 qh, qh->device_us,
530 DWC2_ROUND_US_TO_SLICE(qh->device_us),
531 DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
532
533 if (map) {
534 dwc2_sch_dbg(hsotg,
535 "QH=%p Whole low/full speed map %p now:\n",
536 qh, map);
537 pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
538 DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
539 dwc2_qh_print, &print_data);
540 }
541 }
542
543 for (i = 0; i < qh->num_hs_transfers; i++) {
544 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
545 int uframe = trans_time->start_schedule_us /
546 DWC2_HS_PERIODIC_US_PER_UFRAME;
547 int rel_us = trans_time->start_schedule_us %
548 DWC2_HS_PERIODIC_US_PER_UFRAME;
549
550 dwc2_sch_dbg(hsotg,
551 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
552 qh, i, trans_time->duration_us, uframe, rel_us);
553 }
554 if (qh->num_hs_transfers) {
555 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
556 pmap_print(hsotg->hs_periodic_bitmap,
557 DWC2_HS_PERIODIC_US_PER_UFRAME,
558 DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
559 dwc2_qh_print, &print_data);
560 }
561
562}
563
564/**
565 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
566 *
567 * @hsotg: The HCD state structure for the DWC OTG controller.
568 * @qh: QH for the periodic transfer.
569 * @search_slice: We'll start trying to schedule at the passed slice.
570 * Remember that slices are the units of the low speed
571 * schedule (think 25us or so).
572 *
573 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
574 *
575 * Normally we schedule low speed devices on the map associated with the TT.
576 *
577 * Returns: 0 for success or an error code.
578 */
579static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
580 int search_slice)
581{
582 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
583 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
584 int slice;
585
586 if (map == NULL)
587 return -EINVAL;
588
589 /*
590 * Schedule on the proper low speed map with our low speed scheduling
591 * parameters. Note that we use the "device_interval" here since
592 * we want the low speed interval and the only way we'd be in this
593 * function is if the device is low speed.
594 *
595 * If we happen to be doing low speed and high speed scheduling for the
596 * same transaction (AKA we have a split) we always do low speed first.
597 * That means we can always pass "false" for only_one_period (that
598 * parameters is only useful when we're trying to get one schedule to
599 * match what we already planned in the other schedule).
600 */
601 slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
602 DWC2_LS_SCHEDULE_FRAMES, slices,
603 qh->device_interval, search_slice, false);
604
605 if (slice < 0)
606 return slice;
607
608 qh->ls_start_schedule_slice = slice;
609 return 0;
610}
611
612/**
613 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
614 *
615 * @hsotg: The HCD state structure for the DWC OTG controller.
616 * @qh: QH for the periodic transfer.
617 */
618static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
619 struct dwc2_qh *qh)
620{
621 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
622 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
623
624 /* Schedule should have failed, so no worries about no error code */
625 if (map == NULL)
626 return;
627
628 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
629 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
630 qh->ls_start_schedule_slice);
631}
632
633/**
634 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
635 *
636 * This will schedule something on the main dwc2 schedule.
637 *
638 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
639 * update this with the result upon success. We also use the duration from
640 * the same structure.
641 *
642 * @hsotg: The HCD state structure for the DWC OTG controller.
643 * @qh: QH for the periodic transfer.
644 * @only_one_period: If true we will limit ourselves to just looking at
645 * one period (aka one 100us chunk). This is used if we have
646 * already scheduled something on the low speed schedule and
647 * need to find something that matches on the high speed one.
648 * @index: The index into qh->hs_transfers that we're working with.
649 *
650 * Returns: 0 for success or an error code. Upon success the
651 * dwc2_hs_transfer_time specified by "index" will be updated.
652 */
653static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
654 bool only_one_period, int index)
655{
656 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
657 int us;
658
659 us = pmap_schedule(hsotg->hs_periodic_bitmap,
660 DWC2_HS_PERIODIC_US_PER_UFRAME,
661 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
662 qh->host_interval, trans_time->start_schedule_us,
663 only_one_period);
664
665 if (us < 0)
666 return us;
667
668 trans_time->start_schedule_us = us;
669 return 0;
670}
671
672/**
673 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
674 *
675 * @hsotg: The HCD state structure for the DWC OTG controller.
676 * @qh: QH for the periodic transfer.
677 */
678static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
679 struct dwc2_qh *qh, int index)
680{
681 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
682
683 pmap_unschedule(hsotg->hs_periodic_bitmap,
684 DWC2_HS_PERIODIC_US_PER_UFRAME,
685 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
686 qh->host_interval, trans_time->start_schedule_us);
687}
688
689/**
690 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
691 *
692 * This is the most complicated thing in USB. We have to find matching time
693 * in both the global high speed schedule for the port and the low speed
694 * schedule for the TT associated with the given device.
695 *
696 * Being here means that the host must be running in high speed mode and the
697 * device is in low or full speed mode (and behind a hub).
698 *
699 * @hsotg: The HCD state structure for the DWC OTG controller.
700 * @qh: QH for the periodic transfer.
701 */
702static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
703 struct dwc2_qh *qh)
704{
705 int bytecount = dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
706 int ls_search_slice;
707 int err = 0;
708 int host_interval_in_sched;
709
710 /*
711 * The interval (how often to repeat) in the actual host schedule.
712 * See pmap_schedule() for gcd() explanation.
713 */
714 host_interval_in_sched = gcd(qh->host_interval,
715 DWC2_HS_SCHEDULE_UFRAMES);
716
717 /*
718 * We always try to find space in the low speed schedule first, then
719 * try to find high speed time that matches. If we don't, we'll bump
720 * up the place we start searching in the low speed schedule and try
721 * again. To start we'll look right at the beginning of the low speed
722 * schedule.
723 *
724 * Note that this will tend to front-load the high speed schedule.
725 * We may eventually want to try to avoid this by either considering
726 * both schedules together or doing some sort of round robin.
727 */
728 ls_search_slice = 0;
729
730 while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
731 int start_s_uframe;
732 int ssplit_s_uframe;
733 int second_s_uframe;
734 int rel_uframe;
735 int first_count;
736 int middle_count;
737 int end_count;
738 int first_data_bytes;
739 int other_data_bytes;
740 int i;
741
742 if (qh->schedule_low_speed) {
743 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
744
745 /*
746 * If we got an error here there's no other magic we
747 * can do, so bail. All the looping above is only
748 * helpful to redo things if we got a low speed slot
749 * and then couldn't find a matching high speed slot.
750 */
751 if (err)
752 return err;
753 } else {
754 /* Must be missing the tt structure? Why? */
755 WARN_ON_ONCE(1);
756 }
757
758 /*
759 * This will give us a number 0 - 7 if
760 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
761 */
762 start_s_uframe = qh->ls_start_schedule_slice /
763 DWC2_SLICES_PER_UFRAME;
764
765 /* Get a number that's always 0 - 7 */
766 rel_uframe = (start_s_uframe % 8);
767
768 /*
769 * If we were going to start in uframe 7 then we would need to
770 * issue a start split in uframe 6, which spec says is not OK.
771 * Move on to the next full frame (assuming there is one).
772 *
773 * See 11.18.4 Host Split Transaction Scheduling Requirements
774 * bullet 1.
775 */
776 if (rel_uframe == 7) {
777 if (qh->schedule_low_speed)
778 dwc2_ls_pmap_unschedule(hsotg, qh);
779 ls_search_slice =
780 (qh->ls_start_schedule_slice /
781 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
782 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
186 continue; 783 continue;
784 }
187 785
188 /* 786 /*
189 * we need n consecutive slots so use j as a start slot 787 * For ISOC in:
190 * j plus j+1 must be enough time (for now) 788 * - start split (frame -1)
789 * - complete split w/ data (frame +1)
790 * - complete split w/ data (frame +2)
791 * - ...
792 * - complete split w/ data (frame +num_data_packets)
793 * - complete split w/ data (frame +num_data_packets+1)
794 * - complete split w/ data (frame +num_data_packets+2, max 8)
795 * ...though if frame was "0" then max is 7...
796 *
797 * For ISOC out we might need to do:
798 * - start split w/ data (frame -1)
799 * - start split w/ data (frame +0)
800 * - ...
801 * - start split w/ data (frame +num_data_packets-2)
802 *
803 * For INTERRUPT in we might need to do:
804 * - start split (frame -1)
805 * - complete split w/ data (frame +1)
806 * - complete split w/ data (frame +2)
807 * - complete split w/ data (frame +3, max 8)
808 *
809 * For INTERRUPT out we might need to do:
810 * - start split w/ data (frame -1)
811 * - complete split (frame +1)
812 * - complete split (frame +2)
813 * - complete split (frame +3, max 8)
814 *
815 * Start adjusting!
191 */ 816 */
192 xtime = hsotg->frame_usecs[i]; 817 ssplit_s_uframe = (start_s_uframe +
193 for (j = i + 1; j < 8; j++) { 818 host_interval_in_sched - 1) %
194 /* 819 host_interval_in_sched;
195 * if we add this frame remaining time to xtime we may 820 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
196 * be OK, if not we need to test j for a complete frame 821 second_s_uframe = start_s_uframe;
197 */ 822 else
198 if (xtime + hsotg->frame_usecs[j] < utime) { 823 second_s_uframe = start_s_uframe + 1;
199 if (hsotg->frame_usecs[j] < 824
200 max_uframe_usecs[j]) 825 /* First data transfer might not be all 188 bytes. */
201 continue; 826 first_data_bytes = 188 -
827 DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
828 DWC2_SLICES_PER_UFRAME),
829 DWC2_SLICES_PER_UFRAME);
830 if (first_data_bytes > bytecount)
831 first_data_bytes = bytecount;
832 other_data_bytes = bytecount - first_data_bytes;
833
834 /*
835 * For now, skip OUT xfers where first xfer is partial
836 *
837 * Main dwc2 code assumes:
838 * - INT transfers never get split in two.
839 * - ISOC transfers can always transfer 188 bytes the first
840 * time.
841 *
842 * Until that code is fixed, try again if the first transfer
843 * couldn't transfer everything.
844 *
845 * This code can be removed if/when the rest of dwc2 handles
846 * the above cases. Until it's fixed we just won't be able
847 * to schedule quite as tightly.
848 */
849 if (!qh->ep_is_in &&
850 (first_data_bytes != min_t(int, 188, bytecount))) {
851 dwc2_sch_dbg(hsotg,
852 "QH=%p avoiding broken 1st xfer (%d, %d)\n",
853 qh, first_data_bytes, bytecount);
854 if (qh->schedule_low_speed)
855 dwc2_ls_pmap_unschedule(hsotg, qh);
856 ls_search_slice = (start_s_uframe + 1) *
857 DWC2_SLICES_PER_UFRAME;
858 continue;
859 }
860
861 /* Start by assuming transfers for the bytes */
862 qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
863
864 /*
865 * Everything except ISOC OUT has extra transfers. Rules are
866 * complicated. See 11.18.4 Host Split Transaction Scheduling
867 * Requirements bullet 3.
868 */
869 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
870 if (rel_uframe == 6)
871 qh->num_hs_transfers += 2;
872 else
873 qh->num_hs_transfers += 3;
874
875 if (qh->ep_is_in) {
876 /*
877 * First is start split, middle/end is data.
878 * Allocate full data bytes for all data.
879 */
880 first_count = 4;
881 middle_count = bytecount;
882 end_count = bytecount;
883 } else {
884 /*
885 * First is data, middle/end is complete.
886 * First transfer and second can have data.
887 * Rest should just have complete split.
888 */
889 first_count = first_data_bytes;
890 middle_count = max_t(int, 4, other_data_bytes);
891 end_count = 4;
202 } 892 }
203 if (xtime >= utime) { 893 } else {
204 t_left = utime; 894 if (qh->ep_is_in) {
205 for (k = i; k < 8; k++) { 895 int last;
206 t_left -= hsotg->frame_usecs[k]; 896
207 if (t_left <= 0) { 897 /* Account for the start split */
208 qh->frame_usecs[k] += 898 qh->num_hs_transfers++;
209 hsotg->frame_usecs[k] 899
210 + t_left; 900 /* Calculate "L" value from spec */
211 hsotg->frame_usecs[k] = -t_left; 901 last = rel_uframe + qh->num_hs_transfers + 1;
212 return i; 902
213 } else { 903 /* Start with basic case */
214 qh->frame_usecs[k] += 904 if (last <= 6)
215 hsotg->frame_usecs[k]; 905 qh->num_hs_transfers += 2;
216 hsotg->frame_usecs[k] = 0; 906 else
217 } 907 qh->num_hs_transfers += 1;
218 } 908
909 /* Adjust downwards */
910 if (last >= 6 && rel_uframe == 0)
911 qh->num_hs_transfers--;
912
913 /* 1st = start; rest can contain data */
914 first_count = 4;
915 middle_count = min_t(int, 188, bytecount);
916 end_count = middle_count;
917 } else {
918 /* All contain data, last might be smaller */
919 first_count = first_data_bytes;
920 middle_count = min_t(int, 188,
921 other_data_bytes);
922 end_count = other_data_bytes % 188;
219 } 923 }
220 /* add the frame time to x time */
221 xtime += hsotg->frame_usecs[j];
222 /* we must have a fully available next frame or break */
223 if (xtime < utime &&
224 hsotg->frame_usecs[j] == max_uframe_usecs[j])
225 continue;
226 } 924 }
925
926 /* Assign durations per uFrame */
927 qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
928 for (i = 1; i < qh->num_hs_transfers - 1; i++)
929 qh->hs_transfers[i].duration_us =
930 HS_USECS_ISO(middle_count);
931 if (qh->num_hs_transfers > 1)
932 qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
933 HS_USECS_ISO(end_count);
934
935 /*
936 * Assign start us. The call below to dwc2_hs_pmap_schedule()
937 * will start with these numbers but may adjust within the same
938 * microframe.
939 */
940 qh->hs_transfers[0].start_schedule_us =
941 ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
942 for (i = 1; i < qh->num_hs_transfers; i++)
943 qh->hs_transfers[i].start_schedule_us =
944 ((second_s_uframe + i - 1) %
945 DWC2_HS_SCHEDULE_UFRAMES) *
946 DWC2_HS_PERIODIC_US_PER_UFRAME;
947
948 /* Try to schedule with filled in hs_transfers above */
949 for (i = 0; i < qh->num_hs_transfers; i++) {
950 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
951 if (err)
952 break;
953 }
954
955 /* If we scheduled all w/out breaking out then we're all good */
956 if (i == qh->num_hs_transfers)
957 break;
958
959 for (; i >= 0; i--)
960 dwc2_hs_pmap_unschedule(hsotg, qh, i);
961
962 if (qh->schedule_low_speed)
963 dwc2_ls_pmap_unschedule(hsotg, qh);
964
965 /* Try again starting in the next microframe */
966 ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
227 } 967 }
228 return -ENOSPC; 968
969 if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
970 return -ENOSPC;
971
972 return 0;
229} 973}
230 974
231static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 975/**
976 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
977 *
978 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
979 * interface.
980 *
981 * @hsotg: The HCD state structure for the DWC OTG controller.
982 * @qh: QH for the periodic transfer.
983 */
984static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
985{
986 /* In non-split host and device time are the same */
987 WARN_ON(qh->host_us != qh->device_us);
988 WARN_ON(qh->host_interval != qh->device_interval);
989 WARN_ON(qh->num_hs_transfers != 1);
990
991 /* We'll have one transfer; init start to 0 before calling scheduler */
992 qh->hs_transfers[0].start_schedule_us = 0;
993 qh->hs_transfers[0].duration_us = qh->host_us;
994
995 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
996}
997
998/**
999 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
1000 *
1001 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
1002 * interface.
1003 *
1004 * @hsotg: The HCD state structure for the DWC OTG controller.
1005 * @qh: QH for the periodic transfer.
1006 */
1007static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1008{
1009 /* In non-split host and device time are the same */
1010 WARN_ON(qh->host_us != qh->device_us);
1011 WARN_ON(qh->host_interval != qh->device_interval);
1012 WARN_ON(!qh->schedule_low_speed);
1013
1014 /* Run on the main low speed schedule (no split = no hub = no TT) */
1015 return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1016}
1017
1018/**
1019 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
1020 *
1021 * Calls one of the 3 sub-function depending on what type of transfer this QH
1022 * is for. Also adds some printing.
1023 *
1024 * @hsotg: The HCD state structure for the DWC OTG controller.
1025 * @qh: QH for the periodic transfer.
1026 */
1027static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
232{ 1028{
233 int ret; 1029 int ret;
234 1030
235 if (qh->dev_speed == USB_SPEED_HIGH) { 1031 if (qh->dev_speed == USB_SPEED_HIGH)
236 /* if this is a hs transaction we need a full frame */ 1032 ret = dwc2_uframe_schedule_hs(hsotg, qh);
237 ret = dwc2_find_single_uframe(hsotg, qh); 1033 else if (!qh->do_split)
238 } else { 1034 ret = dwc2_uframe_schedule_ls(hsotg, qh);
239 /* 1035 else
240 * if this is a fs transaction we may need a sequence 1036 ret = dwc2_uframe_schedule_split(hsotg, qh);
241 * of frames 1037
242 */ 1038 if (ret)
243 ret = dwc2_find_multi_uframe(hsotg, qh); 1039 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
244 } 1040 else
1041 dwc2_qh_schedule_print(hsotg, qh);
1042
245 return ret; 1043 return ret;
246} 1044}
247 1045
248/** 1046/**
1047 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
1048 *
1049 * @hsotg: The HCD state structure for the DWC OTG controller.
1050 * @qh: QH for the periodic transfer.
1051 */
1052static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1053{
1054 int i;
1055
1056 for (i = 0; i < qh->num_hs_transfers; i++)
1057 dwc2_hs_pmap_unschedule(hsotg, qh, i);
1058
1059 if (qh->schedule_low_speed)
1060 dwc2_ls_pmap_unschedule(hsotg, qh);
1061
1062 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1063}
1064
1065/**
249 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled 1066 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
250 * 1067 *
251 * Takes a qh that has already been scheduled (which means we know we have the 1068 * Takes a qh that has already been scheduled (which means we know we have the
@@ -265,6 +1082,7 @@ static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
265 u16 frame_number; 1082 u16 frame_number;
266 u16 earliest_frame; 1083 u16 earliest_frame;
267 u16 next_active_frame; 1084 u16 next_active_frame;
1085 u16 relative_frame;
268 u16 interval; 1086 u16 interval;
269 1087
270 /* 1088 /*
@@ -292,8 +1110,36 @@ static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
292 goto exit; 1110 goto exit;
293 } 1111 }
294 1112
295 /* Adjust interval as per high speed schedule which has 8 uFrame */ 1113 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
296 interval = gcd(qh->host_interval, 8); 1114 /*
1115 * We're either at high speed or we're doing a split (which
1116 * means we're talking high speed to a hub). In any case
1117 * the first frame should be based on when the first scheduled
1118 * event is.
1119 */
1120 WARN_ON(qh->num_hs_transfers < 1);
1121
1122 relative_frame = qh->hs_transfers[0].start_schedule_us /
1123 DWC2_HS_PERIODIC_US_PER_UFRAME;
1124
1125 /* Adjust interval as per high speed schedule */
1126 interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
1127
1128 } else {
1129 /*
1130 * Low or full speed directly on dwc2. Just about the same
1131 * as high speed but on a different schedule and with slightly
1132 * different adjustments. Note that this works because when
1133 * the host and device are both low speed then frames in the
1134 * controller tick at low speed.
1135 */
1136 relative_frame = qh->ls_start_schedule_slice /
1137 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
1138 interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
1139 }
1140
1141 /* Scheduler messed up if frame is past interval */
1142 WARN_ON(relative_frame >= interval);
297 1143
298 /* 1144 /*
299 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've 1145 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
@@ -310,7 +1156,7 @@ static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
310 * scheduled for. 1156 * scheduled for.
311 */ 1157 */
312 next_active_frame = dwc2_frame_num_inc(next_active_frame, 1158 next_active_frame = dwc2_frame_num_inc(next_active_frame,
313 qh->assigned_uframe); 1159 relative_frame);
314 1160
315 /* 1161 /*
316 * We actually need 1 frame before since the next_active_frame is 1162 * We actually need 1 frame before since the next_active_frame is
@@ -351,9 +1197,7 @@ static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
351 int status; 1197 int status;
352 1198
353 if (hsotg->core_params->uframe_sched > 0) { 1199 if (hsotg->core_params->uframe_sched > 0) {
354 status = dwc2_find_uframe(hsotg, qh); 1200 status = dwc2_uframe_schedule(hsotg, qh);
355 if (status >= 0)
356 qh->assigned_uframe = status;
357 } else { 1201 } else {
358 status = dwc2_periodic_channel_available(hsotg); 1202 status = dwc2_periodic_channel_available(hsotg);
359 if (status) { 1203 if (status) {
@@ -410,12 +1254,7 @@ static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
410 hsotg->periodic_usecs -= qh->host_us; 1254 hsotg->periodic_usecs -= qh->host_us;
411 1255
412 if (hsotg->core_params->uframe_sched > 0) { 1256 if (hsotg->core_params->uframe_sched > 0) {
413 int i; 1257 dwc2_uframe_unschedule(hsotg, qh);
414
415 for (i = 0; i < 8; i++) {
416 hsotg->frame_usecs[i] += qh->frame_usecs[i];
417 qh->frame_usecs[i] = 0;
418 }
419 } else { 1258 } else {
420 /* Release periodic channel reservation */ 1259 /* Release periodic channel reservation */
421 hsotg->periodic_channels--; 1260 hsotg->periodic_channels--;
@@ -606,88 +1445,81 @@ static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
606 * @qh: The QH to init 1445 * @qh: The QH to init
607 * @urb: Holds the information about the device/endpoint needed to initialize 1446 * @urb: Holds the information about the device/endpoint needed to initialize
608 * the QH 1447 * the QH
1448 * @mem_flags: Flags for allocating memory.
609 */ 1449 */
610static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 1450static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
611 struct dwc2_hcd_urb *urb) 1451 struct dwc2_hcd_urb *urb, gfp_t mem_flags)
612{ 1452{
613 int dev_speed, hub_addr, hub_port; 1453 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1454 u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1455 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1456 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1457 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1458 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
1459 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1460 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1461 dev_speed != USB_SPEED_HIGH);
1462 int maxp = dwc2_hcd_get_mps(&urb->pipe_info);
1463 int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp);
614 char *speed, *type; 1464 char *speed, *type;
615 1465
616 dev_vdbg(hsotg->dev, "%s()\n", __func__);
617
618 /* Initialize QH */ 1466 /* Initialize QH */
619 qh->hsotg = hsotg; 1467 qh->hsotg = hsotg;
620 setup_timer(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 1468 setup_timer(&qh->unreserve_timer, dwc2_unreserve_timer_fn,
621 (unsigned long)qh); 1469 (unsigned long)qh);
622 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1470 qh->ep_type = ep_type;
623 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 1471 qh->ep_is_in = ep_is_in;
624 1472
625 qh->data_toggle = DWC2_HC_PID_DATA0; 1473 qh->data_toggle = DWC2_HC_PID_DATA0;
626 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 1474 qh->maxp = maxp;
627 INIT_LIST_HEAD(&qh->qtd_list); 1475 INIT_LIST_HEAD(&qh->qtd_list);
628 INIT_LIST_HEAD(&qh->qh_list_entry); 1476 INIT_LIST_HEAD(&qh->qh_list_entry);
629 1477
630 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 1478 qh->do_split = do_split;
631 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 1479 qh->dev_speed = dev_speed;
1480
1481 if (ep_is_int || ep_is_isoc) {
1482 /* Compute scheduling parameters once and save them */
1483 int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
1484 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1485 mem_flags,
1486 &qh->ttport);
1487 int device_ns;
632 1488
633 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 1489 qh->dwc_tt = dwc_tt;
634 1490
635 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 1491 qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
636 hub_addr != 0 && hub_addr != 1) { 1492 ep_is_isoc, bytecount));
637 dev_vdbg(hsotg->dev, 1493 device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
638 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 1494 ep_is_isoc, bytecount);
639 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
640 hub_port);
641 qh->do_split = 1;
642 }
643 1495
644 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 1496 if (do_split && dwc_tt)
645 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 1497 device_ns += dwc_tt->usb_tt->think_time;
646 /* Compute scheduling parameters once and save them */ 1498 qh->device_us = NS_TO_US(device_ns);
647 u32 hprt, prtspd;
648
649 /* Todo: Account for split transfers in the bus time */
650 int bytecount =
651 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
652
653 qh->host_us = NS_TO_US(usb_calc_bus_time(qh->do_split ?
654 USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
655 qh->ep_type == USB_ENDPOINT_XFER_ISOC,
656 bytecount));
657
658 qh->host_interval = urb->interval;
659 dwc2_sch_dbg(hsotg, "QH=%p init nxt=%04x, fn=%04x, int=%#x\n",
660 qh, qh->next_active_frame, hsotg->frame_number,
661 qh->host_interval);
662#if 0
663 /* Increase interrupt polling rate for debugging */
664 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
665 qh->host_interval = 8;
666#endif
667 hprt = dwc2_readl(hsotg->regs + HPRT0);
668 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
669 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
670 (dev_speed == USB_SPEED_LOW ||
671 dev_speed == USB_SPEED_FULL)) {
672 qh->host_interval *= 8;
673 dwc2_sch_dbg(hsotg,
674 "QH=%p init*8 nxt=%04x, fn=%04x, int=%#x\n",
675 qh, qh->next_active_frame,
676 hsotg->frame_number, qh->host_interval);
677 1499
678 }
679 dev_dbg(hsotg->dev, "interval=%d\n", qh->host_interval);
680 }
681 1500
682 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 1501 qh->device_interval = urb->interval;
683 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 1502 qh->host_interval = urb->interval * (do_split ? 8 : 1);
684 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
685 dwc2_hcd_get_dev_addr(&urb->pipe_info));
686 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
687 dwc2_hcd_get_ep_num(&urb->pipe_info),
688 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
689 1503
690 qh->dev_speed = dev_speed; 1504 /*
1505 * Schedule low speed if we're running the host in low or
1506 * full speed OR if we've got a "TT" to deal with to access this
1507 * device.
1508 */
1509 qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
1510 dwc_tt;
1511
1512 if (do_split) {
1513 /* We won't know num transfers until we schedule */
1514 qh->num_hs_transfers = -1;
1515 } else if (dev_speed == USB_SPEED_HIGH) {
1516 qh->num_hs_transfers = 1;
1517 } else {
1518 qh->num_hs_transfers = 0;
1519 }
1520
1521 /* We'll schedule later when we have something to do */
1522 }
691 1523
692 switch (dev_speed) { 1524 switch (dev_speed) {
693 case USB_SPEED_LOW: 1525 case USB_SPEED_LOW:
@@ -703,7 +1535,6 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
703 speed = "?"; 1535 speed = "?";
704 break; 1536 break;
705 } 1537 }
706 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
707 1538
708 switch (qh->ep_type) { 1539 switch (qh->ep_type) {
709 case USB_ENDPOINT_XFER_ISOC: 1540 case USB_ENDPOINT_XFER_ISOC:
@@ -723,13 +1554,21 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
723 break; 1554 break;
724 } 1555 }
725 1556
726 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 1557 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
727 1558 speed, bytecount);
728 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 1559 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
729 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 1560 dwc2_hcd_get_dev_addr(&urb->pipe_info),
730 qh->host_us); 1561 dwc2_hcd_get_ep_num(&urb->pipe_info),
731 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 1562 ep_is_in ? "IN" : "OUT");
732 qh->host_interval); 1563 if (ep_is_int || ep_is_isoc) {
1564 dwc2_sch_dbg(hsotg,
1565 "QH=%p ...duration: host=%d us, device=%d us\n",
1566 qh, qh->host_us, qh->device_us);
1567 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1568 qh, qh->host_interval, qh->device_interval);
1569 if (qh->schedule_low_speed)
1570 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1571 qh, dwc2_get_ls_map(hsotg, qh));
733 } 1572 }
734} 1573}
735 1574
@@ -757,7 +1596,7 @@ struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
757 if (!qh) 1596 if (!qh)
758 return NULL; 1597 return NULL;
759 1598
760 dwc2_qh_init(hsotg, qh, urb); 1599 dwc2_qh_init(hsotg, qh, urb, mem_flags);
761 1600
762 if (hsotg->core_params->dma_desc_enable > 0 && 1601 if (hsotg->core_params->dma_desc_enable > 0 &&
763 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 1602 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
@@ -789,6 +1628,7 @@ void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
789 dwc2_do_unreserve(hsotg, qh); 1628 dwc2_do_unreserve(hsotg, qh);
790 spin_unlock_irqrestore(&hsotg->lock, flags); 1629 spin_unlock_irqrestore(&hsotg->lock, flags);
791 } 1630 }
1631 dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
792 1632
793 if (qh->desc_list) 1633 if (qh->desc_list)
794 dwc2_hcd_qh_free_ddma(hsotg, qh); 1634 dwc2_hcd_qh_free_ddma(hsotg, qh);
@@ -904,6 +1744,8 @@ static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
904 u16 incr; 1744 u16 incr;
905 1745
906 /* 1746 /*
1747 * See dwc2_uframe_schedule_split() for split scheduling.
1748 *
907 * Basically: increment 1 normally, but 2 right after the start split 1749 * Basically: increment 1 normally, but 2 right after the start split
908 * (except for ISOC out). 1750 * (except for ISOC out).
909 */ 1751 */
@@ -1006,9 +1848,17 @@ static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1006 if (qh->start_active_frame == qh->next_active_frame || 1848 if (qh->start_active_frame == qh->next_active_frame ||
1007 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) { 1849 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1008 u16 ideal_start = qh->start_active_frame; 1850 u16 ideal_start = qh->start_active_frame;
1851 int periods_in_map;
1009 1852
1010 /* Adjust interval as per gcd with plan length. */ 1853 /*
1011 interval = gcd(interval, 8); 1854 * Adjust interval as per gcd with map size.
1855 * See pmap_schedule() for more details here.
1856 */
1857 if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
1858 periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
1859 else
1860 periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
1861 interval = gcd(interval, periods_in_map);
1012 1862
1013 do { 1863 do {
1014 qh->start_active_frame = dwc2_frame_num_inc( 1864 qh->start_active_frame = dwc2_frame_num_inc(
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-16 10:00:12 -0400