Merge tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB/PHY updates from Greg KH:
 "Here is the big set of USB and PHY driver patches for 5.2-rc1

  There is the usual set of:

   - USB gadget updates

   - PHY driver updates and additions

   - USB serial driver updates and fixes

   - typec updates and new chips supported

   - mtu3 driver updates

   - xhci driver updates

   - other tiny driver updates

  Nothing really interesting, just constant forward progress.

  All of these have been in linux-next for a while with no reported
  issues. The usb-gadget and usb-serial trees were merged a bit "late",
  but both of them had been in linux-next before they got merged here
  last Friday"

* tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits)
  USB: serial: f81232: implement break control
  USB: serial: f81232: add high baud rate support
  USB: serial: f81232: clear overrun flag
  USB: serial: f81232: fix interrupt worker not stop
  usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA
  usb: dwc3: Fix default lpm_nyet_threshold value
  usb: dwc3: debug: Print GET_STATUS(device) tracepoint
  usb: dwc3: Do core validation early on probe
  usb: dwc3: gadget: Set lpm_capable
  usb: gadget: atmel: tie wake lock to running clock
  usb: gadget: atmel: support USB suspend
  usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask
  dwc2: gadget: Fix completed transfer size calculation in DDMA
  usb: dwc2: Set lpm mode parameters depend on HW configuration
  usb: dwc2: Fix channel disable flow
  usb: dwc2: Set actual frame number for completed ISOC transfer
  usb: gadget: do not use __constant_cpu_to_le16
  usb: dwc2: gadget: Increase descriptors count for ISOC's
  usb: introduce usb_ep_type_string() function
  usb: dwc3: move synchronize_irq() out of the spinlock protected block
  ...

1 files changed, 88 insertions, 238 deletions

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 3f087962f498..b50ec3714fd8 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -97,196 +97,6 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
         dwc2_writel(hsotg, intmsk, GINTMSK);
 }
 
-/*
- * Initializes the FSLSPClkSel field of the HCFG register depending on the
- * PHY type
- */
-static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
-{
-        u32 hcfg, val;
-
-        if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
-             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
-             hsotg->params.ulpi_fs_ls) ||
-            hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
-                /* Full speed PHY */
-                val = HCFG_FSLSPCLKSEL_48_MHZ;
-        } else {
-                /* High speed PHY running at full speed or high speed */
-                val = HCFG_FSLSPCLKSEL_30_60_MHZ;
-        }
-
-        dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
-        hcfg = dwc2_readl(hsotg, HCFG);
-        hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
-        hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
-        dwc2_writel(hsotg, hcfg, HCFG);
-}
-
-static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
-{
-        u32 usbcfg, ggpio, i2cctl;
-        int retval = 0;
-
-        /*
-         * core_init() is now called on every switch so only call the
-         * following for the first time through
-         */
-        if (select_phy) {
-                dev_dbg(hsotg->dev, "FS PHY selected\n");
-
-                usbcfg = dwc2_readl(hsotg, GUSBCFG);
-                if (!(usbcfg & GUSBCFG_PHYSEL)) {
-                        usbcfg |= GUSBCFG_PHYSEL;
-                        dwc2_writel(hsotg, usbcfg, GUSBCFG);
-
-                        /* Reset after a PHY select */
-                        retval = dwc2_core_reset(hsotg, false);
-
-                        if (retval) {
-                                dev_err(hsotg->dev,
-                                        "%s: Reset failed, aborting", __func__);
-                                return retval;
-                        }
-                }
-
-                if (hsotg->params.activate_stm_fs_transceiver) {
-                        ggpio = dwc2_readl(hsotg, GGPIO);
-                        if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
-                                dev_dbg(hsotg->dev, "Activating transceiver\n");
-                                /*
-                                 * STM32F4x9 uses the GGPIO register as general
-                                 * core configuration register.
-                                 */
-                                ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
-                                dwc2_writel(hsotg, ggpio, GGPIO);
-                        }
-                }
-        }
-
-        /*
-         * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
-         * do this on HNP Dev/Host mode switches (done in dev_init and
-         * host_init).
-         */
-        if (dwc2_is_host_mode(hsotg))
-                dwc2_init_fs_ls_pclk_sel(hsotg);
-
-        if (hsotg->params.i2c_enable) {
-                dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
-
-                /* Program GUSBCFG.OtgUtmiFsSel to I2C */
-                usbcfg = dwc2_readl(hsotg, GUSBCFG);
-                usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
-                dwc2_writel(hsotg, usbcfg, GUSBCFG);
-
-                /* Program GI2CCTL.I2CEn */
-                i2cctl = dwc2_readl(hsotg, GI2CCTL);
-                i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
-                i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
-                i2cctl &= ~GI2CCTL_I2CEN;
-                dwc2_writel(hsotg, i2cctl, GI2CCTL);
-                i2cctl |= GI2CCTL_I2CEN;
-                dwc2_writel(hsotg, i2cctl, GI2CCTL);
-        }
-
-        return retval;
-}
-
-static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
-{
-        u32 usbcfg, usbcfg_old;
-        int retval = 0;
-
-        if (!select_phy)
-                return 0;
-
-        usbcfg = dwc2_readl(hsotg, GUSBCFG);
-        usbcfg_old = usbcfg;
-
-        /*
-         * HS PHY parameters. These parameters are preserved during soft reset
-         * so only program the first time. Do a soft reset immediately after
-         * setting phyif.
-         */
-        switch (hsotg->params.phy_type) {
-        case DWC2_PHY_TYPE_PARAM_ULPI:
-                /* ULPI interface */
-                dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
-                usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
-                usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
-                if (hsotg->params.phy_ulpi_ddr)
-                        usbcfg |= GUSBCFG_DDRSEL;
-
-                /* Set external VBUS indicator as needed. */
-                if (hsotg->params.oc_disable)
-                        usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
-                                   GUSBCFG_INDICATORPASSTHROUGH);
-                break;
-        case DWC2_PHY_TYPE_PARAM_UTMI:
-                /* UTMI+ interface */
-                dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
-                usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
-                if (hsotg->params.phy_utmi_width == 16)
-                        usbcfg |= GUSBCFG_PHYIF16;
-                break;
-        default:
-                dev_err(hsotg->dev, "FS PHY selected at HS!\n");
-                break;
-        }
-
-        if (usbcfg != usbcfg_old) {
-                dwc2_writel(hsotg, usbcfg, GUSBCFG);
-
-                /* Reset after setting the PHY parameters */
-                retval = dwc2_core_reset(hsotg, false);
-                if (retval) {
-                        dev_err(hsotg->dev,
-                                "%s: Reset failed, aborting", __func__);
-                        return retval;
-                }
-        }
-
-        return retval;
-}
-
-static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
-{
-        u32 usbcfg;
-        int retval = 0;
-
-        if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
-             hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
-            hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
-                /* If FS/LS mode with FS/LS PHY */
-                retval = dwc2_fs_phy_init(hsotg, select_phy);
-                if (retval)
-                        return retval;
-        } else {
-                /* High speed PHY */
-                retval = dwc2_hs_phy_init(hsotg, select_phy);
-                if (retval)
-                        return retval;
-        }
-
-        if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
-            hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
-            hsotg->params.ulpi_fs_ls) {
-                dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
-                usbcfg = dwc2_readl(hsotg, GUSBCFG);
-                usbcfg |= GUSBCFG_ULPI_FS_LS;
-                usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
-                dwc2_writel(hsotg, usbcfg, GUSBCFG);
-        } else {
-                usbcfg = dwc2_readl(hsotg, GUSBCFG);
-                usbcfg &= ~GUSBCFG_ULPI_FS_LS;
-                usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
-                dwc2_writel(hsotg, usbcfg, GUSBCFG);
-        }
-
-        return retval;
-}
-
 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 {
         u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
@@ -2437,25 +2247,31 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
                 num_channels = hsotg->params.host_channels;
                 for (i = 0; i < num_channels; i++) {
                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
-                        hcchar &= ~HCCHAR_CHENA;
-                        hcchar |= HCCHAR_CHDIS;
-                        hcchar &= ~HCCHAR_EPDIR;
-                        dwc2_writel(hsotg, hcchar, HCCHAR(i));
+                        if (hcchar & HCCHAR_CHENA) {
+                                hcchar &= ~HCCHAR_CHENA;
+                                hcchar |= HCCHAR_CHDIS;
+                                hcchar &= ~HCCHAR_EPDIR;
+                                dwc2_writel(hsotg, hcchar, HCCHAR(i));
+                        }
                 }
 
                 /* Halt all channels to put them into a known state */
                 for (i = 0; i < num_channels; i++) {
                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
-                        hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
-                        hcchar &= ~HCCHAR_EPDIR;
-                        dwc2_writel(hsotg, hcchar, HCCHAR(i));
-                        dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
-                                __func__, i);
-
-                        if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
-                                                      HCCHAR_CHENA, 1000)) {
-                                dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
-                                         i);
+                        if (hcchar & HCCHAR_CHENA) {
+                                hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
+                                hcchar &= ~HCCHAR_EPDIR;
+                                dwc2_writel(hsotg, hcchar, HCCHAR(i));
+                                dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
+                                        __func__, i);
+
+                                if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
+                                                              HCCHAR_CHENA,
+                                                              1000)) {
+                                        dev_warn(hsotg->dev,
+                                                 "Unable to clear enable on channel %d\n",
+                                                 i);
+                                }
                         }
                 }
         }
@@ -4376,6 +4192,17 @@ static void dwc2_hcd_reset_func(struct work_struct *work)
         spin_unlock_irqrestore(&hsotg->lock, flags);
 }
 
+static void dwc2_hcd_phy_reset_func(struct work_struct *work)
+{
+        struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
+                                                phy_reset_work);
+        int ret;
+
+        ret = phy_reset(hsotg->phy);
+        if (ret)
+                dev_warn(hsotg->dev, "PHY reset failed\n");
+}
+
 /*
  * =========================================================================
  *  Linux HC Driver Functions
@@ -4471,6 +4298,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
         unsigned long flags;
         int ret = 0;
         u32 hprt0;
+        u32 pcgctl;
 
         spin_lock_irqsave(&hsotg->lock, flags);
 
@@ -4486,7 +4314,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
         if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
                 goto unlock;
 
-        if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
+        if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL)
                 goto skip_power_saving;
 
         /*
@@ -4495,21 +4323,35 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
          */
         if (!hsotg->bus_suspended) {
                 hprt0 = dwc2_read_hprt0(hsotg);
-                hprt0 |= HPRT0_SUSP;
-                hprt0 &= ~HPRT0_PWR;
-                dwc2_writel(hsotg, hprt0, HPRT0);
-                spin_unlock_irqrestore(&hsotg->lock, flags);
-                dwc2_vbus_supply_exit(hsotg);
-                spin_lock_irqsave(&hsotg->lock, flags);
+                if (hprt0 & HPRT0_CONNSTS) {
+                        hprt0 |= HPRT0_SUSP;
+                        if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
+                                hprt0 &= ~HPRT0_PWR;
+                        dwc2_writel(hsotg, hprt0, HPRT0);
+                }
+                if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+                        spin_unlock_irqrestore(&hsotg->lock, flags);
+                        dwc2_vbus_supply_exit(hsotg);
+                        spin_lock_irqsave(&hsotg->lock, flags);
+                } else {
+                        pcgctl = readl(hsotg->regs + PCGCTL);
+                        pcgctl |= PCGCTL_STOPPCLK;
+                        writel(pcgctl, hsotg->regs + PCGCTL);
+                }
         }
 
-        /* Enter partial_power_down */
-        ret = dwc2_enter_partial_power_down(hsotg);
-        if (ret) {
-                if (ret != -ENOTSUPP)
-                        dev_err(hsotg->dev,
-                                "enter partial_power_down failed\n");
-                goto skip_power_saving;
+        if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+                /* Enter partial_power_down */
+                ret = dwc2_enter_partial_power_down(hsotg);
+                if (ret) {
+                        if (ret != -ENOTSUPP)
+                                dev_err(hsotg->dev,
+                                        "enter partial_power_down failed\n");
+                        goto skip_power_saving;
+                }
+
+                /* After entering partial_power_down, hardware is no more accessible */
+                clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
         }
 
         /* Ask phy to be suspended */
@@ -4519,9 +4361,6 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
                 spin_lock_irqsave(&hsotg->lock, flags);
         }
 
-        /* After entering partial_power_down, hardware is no more accessible */
-        clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-
 skip_power_saving:
         hsotg->lx_state = DWC2_L2;
 unlock:
@@ -4534,6 +4373,7 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
 {
         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
         unsigned long flags;
+        u32 pcgctl;
         int ret = 0;
 
         spin_lock_irqsave(&hsotg->lock, flags);
@@ -4544,18 +4384,12 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
         if (hsotg->lx_state != DWC2_L2)
                 goto unlock;
 
-        if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
+        if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
                 hsotg->lx_state = DWC2_L0;
                 goto unlock;
         }
 
         /*
-         * Set HW accessible bit before powering on the controller
-         * since an interrupt may rise.
-         */
-        set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-
-        /*
          * Enable power if not already done.
          * This must not be spinlocked since duration
          * of this call is unknown.
@@ -4566,10 +4400,23 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
                 spin_lock_irqsave(&hsotg->lock, flags);
         }
 
-        /* Exit partial_power_down */
-        ret = dwc2_exit_partial_power_down(hsotg, true);
-        if (ret && (ret != -ENOTSUPP))
-                dev_err(hsotg->dev, "exit partial_power_down failed\n");
+        if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+                /*
+                 * Set HW accessible bit before powering on the controller
+                 * since an interrupt may rise.
+                 */
+                set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+
+                /* Exit partial_power_down */
+                ret = dwc2_exit_partial_power_down(hsotg, true);
+                if (ret && (ret != -ENOTSUPP))
+                        dev_err(hsotg->dev, "exit partial_power_down failed\n");
+        } else {
+                pcgctl = readl(hsotg->regs + PCGCTL);
+                pcgctl &= ~PCGCTL_STOPPCLK;
+                writel(pcgctl, hsotg->regs + PCGCTL);
+        }
 
         hsotg->lx_state = DWC2_L0;
 
@@ -4581,10 +4428,12 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
                 spin_unlock_irqrestore(&hsotg->lock, flags);
                 dwc2_port_resume(hsotg);
         } else {
-                dwc2_vbus_supply_init(hsotg);
+                if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
+                        dwc2_vbus_supply_init(hsotg);
 
-                /* Wait for controller to correctly update D+/D- level */
-                usleep_range(3000, 5000);
+                        /* Wait for controller to correctly update D+/D- level */
+                        usleep_range(3000, 5000);
+                }
 
                 /*
                  * Clear Port Enable and Port Status changes.
@@ -5130,6 +4979,8 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
                 destroy_workqueue(hsotg->wq_otg);
         }
 
+        cancel_work_sync(&hsotg->phy_reset_work);
+
         del_timer(&hsotg->wkp_timer);
 }
 
@@ -5271,11 +5122,10 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
                 hsotg->hc_ptr_array[i] = channel;
         }
 
-        /* Initialize hsotg start work */
+        /* Initialize work */
         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
-
-        /* Initialize port reset work */
         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
+        INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
 
         /*
          * Allocate space for storing data on status transactions. Normally no