usb: dwc2: optionally assert phy reset when waking up

On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit), which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index 19ae2595f1c3..6af6add3d4c0 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -435,6 +435,18 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
                         /* Restart the Phy Clock */
                         pcgcctl &= ~PCGCTL_STOPPCLK;
                         dwc2_writel(hsotg, pcgcctl, PCGCTL);
+
+                        /*
+                         * If we've got this quirk then the PHY is stuck upon
+                         * wakeup.  Assert reset.  This will propagate out and
+                         * eventually we'll re-enumerate the device.  Not great
+                         * but the best we can do.  We can't call phy_reset()
+                         * at interrupt time but there's no hurry, so we'll
+                         * schedule it for later.
+                         */
+                        if (hsotg->reset_phy_on_wake)
+                                dwc2_host_schedule_phy_reset(hsotg);
+
                         mod_timer(&hsotg->wkp_timer,
                                   jiffies + msecs_to_jiffies(71));
                 } else {